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[/] [minsoc/] [trunk/] [backend/] [spartan3e_starter_kit_eth/] [minsoc_bench_defines.v] - Diff between revs 70 and 141

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Rev 70 Rev 141
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`define GENERIC_FPGA
`define GENERIC_FPGA
`define MEMORY_MODEL        //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
`define MEMORY_MODEL        //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
`define NO_CLOCK_DIVISION   //if commented out, generic clock division is implemented (odd divisors are rounded down)
`define NO_CLOCK_DIVISION   //if commented out, generic clock division is implemented (odd divisors are rounded down)
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
 
 
`define FREQ_NUM_FOR_NS 1000000000
`define FREQ_NUM_FOR_NS 100000000
 
 
`define FREQ 10000000
`define FREQ 10000000
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
 
 
`define ETH_PHY_FREQ  25000000
`define ETH_PHY_FREQ  25000000
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`define INITIALIZE_MEMORY_MODEL                 //instantaneously initialize memory model with firmware
`define INITIALIZE_MEMORY_MODEL                 //instantaneously initialize memory model with firmware
                                                                                //only use with the memory model. 
                                                                                //only use with the memory model. 
                                        //If you use the original memory (`define MEMORY_MODEL 
                                        //If you use the original memory (`define MEMORY_MODEL 
                                        //commented out), comment this too.
                                        //commented out), comment this too.
 
 
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`define TEST_UART
 
//`define TEST_ETHERNET
 
 
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