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[/] [minsoc/] [trunk/] [backend/] [spartan3e_starter_kit_eth/] [or1200_defines.v] - Diff between revs 69 and 92

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// By default implementation of l.addc/l.addic
// By default implementation of l.addc/l.addic
// instructions is enabled in case you need them.
// instructions is enabled in case you need them.
// If you don't use them, then disable implementation
// If you don't use them, then disable implementation
// to save area.
// to save area.
//
//
//`define OR1200_IMPL_ADDC
`define OR1200_IMPL_ADDC
 
 
//
//
// Implement l.sub instruction
// Implement l.sub instruction
//
//
// By default implementation of l.sub instructions
// By default implementation of l.sub instructions
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// to be compliant with the simulator. However SR[CY]
// to be compliant with the simulator. However SR[CY]
// is explicitly only used by l.addc/l.addic/l.sub
// is explicitly only used by l.addc/l.addic/l.sub
// instructions and if these three insns are not
// instructions and if these three insns are not
// implemented there is not much point having SR[CY].
// implemented there is not much point having SR[CY].
//
//
//`define OR1200_IMPL_CY
`define OR1200_IMPL_CY
 
 
 
//
 
// Implement carry bit SR[OV]
 
//
 
// Compiler doesn't use this, but other code may like
 
// to.
 
//
 
`define OR1200_IMPL_OV
 
 
 
//
 
// Implement carry bit SR[OVE]
 
//
 
// Overflow interrupt indicator. When enabled, SR[OV] flag
 
// does not remain asserted after exception.
 
//
 
`define OR1200_IMPL_OVE
 
 
 
 
//
//
// Implement rotate in the ALU
// Implement rotate in the ALU
//
//
// At the time of writing this, or32
// At the time of writing this, or32
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//`define OR1200_IMPL_ALU_ROTATE
//`define OR1200_IMPL_ALU_ROTATE
 
 
//
//
// Type of ALU compare to implement
// Type of ALU compare to implement
//
//
// Try either one to find what yields
// Try to find which synthesizes with
// higher clock frequencyin your case.
// most efficient logic use or highest speed.
//
//
//`define OR1200_IMPL_ALU_COMP1
//`define OR1200_IMPL_ALU_COMP1
`define OR1200_IMPL_ALU_COMP2
//`define OR1200_IMPL_ALU_COMP2
 
`define OR1200_IMPL_ALU_COMP3
 
 
//
//
// Implement Find First/Last '1'
// Implement Find First/Last '1'
//
//
`define OR1200_IMPL_ALU_FFL1
`define OR1200_IMPL_ALU_FFL1
 
 
//
//
 
// Implement l.cust5 ALU instruction
 
//
 
//`define OR1200_IMPL_ALU_CUST5
 
 
 
//
 
// Implement l.extXs and l.extXz instructions
 
//
 
`define OR1200_IMPL_ALU_EXT
 
 
 
//
// Implement multiplier
// Implement multiplier
//
//
// By default multiplier is implemented
// By default multiplier is implemented
//
//
`define OR1200_MULT_IMPLEMENTED
`define OR1200_MULT_IMPLEMENTED
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//
//
// Implement HW Single Precision FPU
// Implement HW Single Precision FPU
//
//
//`define OR1200_FPU_IMPLEMENTED
//`define OR1200_FPU_IMPLEMENTED
 
 
 
 
//
//
// Clock ratio RISC clock versus WB clock
// Clock ratio RISC clock versus WB clock
//
//
// If you plan to run WB:RISC clock fixed to 1:1, disable
// If you plan to run WB:RISC clock fixed to 1:1, disable
// both defines
// both defines
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`endif
`endif
 
 
//
//
// ALUOPs
// ALUOPs
//
//
`define OR1200_ALUOP_WIDTH      4
`define OR1200_ALUOP_WIDTH      5
`define OR1200_ALUOP_NOP        4'd4
`define OR1200_ALUOP_NOP        5'b0_0100
/* Order defined by arith insns that have two source operands both in regs
/* LS-nibble encodings correspond to bits [3:0] of instruction */
   (see binutils/include/opcode/or32.h) */
`define OR1200_ALUOP_ADD        5'b0_0000 // 0
`define OR1200_ALUOP_ADD        4'd0
`define OR1200_ALUOP_ADDC       5'b0_0001 // 1
`define OR1200_ALUOP_ADDC       4'd1
`define OR1200_ALUOP_SUB        5'b0_0010 // 2
`define OR1200_ALUOP_SUB        4'd2
`define OR1200_ALUOP_AND        5'b0_0011 // 3
`define OR1200_ALUOP_AND        4'd3
`define OR1200_ALUOP_OR         5'b0_0100 // 4
`define OR1200_ALUOP_OR         4'd4
`define OR1200_ALUOP_XOR        5'b0_0101 // 5
`define OR1200_ALUOP_XOR        4'd5
`define OR1200_ALUOP_MUL        5'b0_0110 // 6
`define OR1200_ALUOP_MUL        4'd6
`define OR1200_ALUOP_RESERVED   5'b0_0111 // 7
`define OR1200_ALUOP_CUST5      4'd7
`define OR1200_ALUOP_SHROT      5'b0_1000 // 8
`define OR1200_ALUOP_SHROT      4'd8
`define OR1200_ALUOP_DIV        5'b0_1001 // 9
`define OR1200_ALUOP_DIV        4'd9
`define OR1200_ALUOP_DIVU       5'b0_1010 // a
`define OR1200_ALUOP_DIVU       4'd10
`define OR1200_ALUOP_MULU       5'b0_1011 // b
`define OR1200_ALUOP_MULU       4'd11
`define OR1200_ALUOP_EXTHB      5'b0_1100 // c
/* Values sent to ALU from decode unit - not strictly defined by ISA */
`define OR1200_ALUOP_EXTW       5'b0_1101 // d
`define OR1200_ALUOP_MOVHI      4'd12
`define OR1200_ALUOP_CMOV       5'b0_1110 // e
`define OR1200_ALUOP_COMP       4'd13
`define OR1200_ALUOP_FFL1       5'b0_1111 // f
`define OR1200_ALUOP_MTSR       4'd14
 
`define OR1200_ALUOP_MFSR       4'd15
/* Values sent to ALU from decode unit - not defined by ISA */
`define OR1200_ALUOP_CMOV       4'd14
`define OR1200_ALUOP_COMP       5'b1_0000 // Comparison
`define OR1200_ALUOP_FFL1       4'd15
`define OR1200_ALUOP_MOVHI      5'b1_0001 // Move-high
 
`define OR1200_ALUOP_CUST5      5'b1_0010 // l.cust5
 
 
// ALU instructions second opcode field (previously multicycle field in 
// ALU instructions second opcode field
// machine word)
`define OR1200_ALUOP2_POS       9:6
`define OR1200_ALUOP2_POS               9:8
`define OR1200_ALUOP2_WIDTH     4
`define OR1200_ALUOP2_WIDTH     2
 
 
 
 
 
//
//
// MACOPs
// MACOPs
//
//
`define OR1200_MACOP_WIDTH      3
`define OR1200_MACOP_WIDTH      3
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`define OR1200_MACOP_MSB        3'b010
`define OR1200_MACOP_MSB        3'b010
 
 
//
//
// Shift/rotate ops
// Shift/rotate ops
//
//
`define OR1200_SHROTOP_WIDTH    2
`define OR1200_SHROTOP_WIDTH    4
`define OR1200_SHROTOP_NOP      2'd0
`define OR1200_SHROTOP_NOP      4'd0
`define OR1200_SHROTOP_SLL      2'd0
`define OR1200_SHROTOP_SLL      4'd0
`define OR1200_SHROTOP_SRL      2'd1
`define OR1200_SHROTOP_SRL      4'd1
`define OR1200_SHROTOP_SRA      2'd2
`define OR1200_SHROTOP_SRA      4'd2
`define OR1200_SHROTOP_ROR      2'd3
`define OR1200_SHROTOP_ROR      4'd3
 
 
 
//
 
// Zero/Sign Extend ops
 
//
 
`define OR1200_EXTHBOP_WIDTH      4
 
`define OR1200_EXTHBOP_BS         4'h1
 
`define OR1200_EXTHBOP_HS         4'h0
 
`define OR1200_EXTHBOP_BZ         4'h3
 
`define OR1200_EXTHBOP_HZ         4'h2
 
`define OR1200_EXTWOP_WIDTH       4
 
`define OR1200_EXTWOP_WS          4'h0
 
`define OR1200_EXTWOP_WZ          4'h1
 
 
// Execution cycles per instruction
// Execution cycles per instruction
`define OR1200_MULTICYCLE_WIDTH 3
`define OR1200_MULTICYCLE_WIDTH 3
`define OR1200_ONE_CYCLE                3'd0
`define OR1200_ONE_CYCLE                3'd0
`define OR1200_TWO_CYCLES               3'd1
`define OR1200_TWO_CYCLES               3'd1
 
 
// Execution control which will "wait on" a module to finish
// Execution control which will "wait on" a module to finish
`define OR1200_WAIT_ON_WIDTH 2
`define OR1200_WAIT_ON_WIDTH 2
`define OR1200_WAIT_ON_FPU `OR1200_WAIT_ON_WIDTH'd1
`define OR1200_WAIT_ON_NOTHING    `OR1200_WAIT_ON_WIDTH'd0
`define OR1200_WAIT_ON_MTSPR `OR1200_WAIT_ON_WIDTH'd2
`define OR1200_WAIT_ON_MULTMAC    `OR1200_WAIT_ON_WIDTH'd1
 
`define OR1200_WAIT_ON_FPU        `OR1200_WAIT_ON_WIDTH'd2
 
`define OR1200_WAIT_ON_MTSPR      `OR1200_WAIT_ON_WIDTH'd3
 
 
 
 
// Operand MUX selects
// Operand MUX selects
`define OR1200_SEL_WIDTH                2
`define OR1200_SEL_WIDTH                2
`define OR1200_SEL_RF                   2'd0
`define OR1200_SEL_RF                   2'd0
`define OR1200_SEL_IMM                  2'd1
`define OR1200_SEL_IMM                  2'd1
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`define OR1200_OR32_JAL               6'b000001
`define OR1200_OR32_JAL               6'b000001
`define OR1200_OR32_BNF               6'b000011
`define OR1200_OR32_BNF               6'b000011
`define OR1200_OR32_BF                6'b000100
`define OR1200_OR32_BF                6'b000100
`define OR1200_OR32_NOP               6'b000101
`define OR1200_OR32_NOP               6'b000101
`define OR1200_OR32_MOVHI             6'b000110
`define OR1200_OR32_MOVHI             6'b000110
 
`define OR1200_OR32_MACRC             6'b000110
`define OR1200_OR32_XSYNC             6'b001000
`define OR1200_OR32_XSYNC             6'b001000
`define OR1200_OR32_RFE               6'b001001
`define OR1200_OR32_RFE               6'b001001
/* */
/* */
`define OR1200_OR32_JR                6'b010001
`define OR1200_OR32_JR                6'b010001
`define OR1200_OR32_JALR              6'b010010
`define OR1200_OR32_JALR              6'b010010
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`define OR1200_OR32_SW                6'b110101
`define OR1200_OR32_SW                6'b110101
`define OR1200_OR32_SB                6'b110110
`define OR1200_OR32_SB                6'b110110
`define OR1200_OR32_SH                6'b110111
`define OR1200_OR32_SH                6'b110111
`define OR1200_OR32_ALU               6'b111000
`define OR1200_OR32_ALU               6'b111000
`define OR1200_OR32_SFXX              6'b111001
`define OR1200_OR32_SFXX              6'b111001
//`define OR1200_OR32_CUST5             6'b111100
`define OR1200_OR32_CUST5             6'b111100
 
 
 
 
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
//
//
// Exceptions
// Exceptions
//
//
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`define OR1200_SR_DME  5
`define OR1200_SR_DME  5
`define OR1200_SR_IME  6
`define OR1200_SR_IME  6
`define OR1200_SR_LEE  7
`define OR1200_SR_LEE  7
`define OR1200_SR_CE   8
`define OR1200_SR_CE   8
`define OR1200_SR_F    9
`define OR1200_SR_F    9
`define OR1200_SR_CY   10       // Unused
`define OR1200_SR_CY   10       // Optional
`define OR1200_SR_OV   11       // Unused
`define OR1200_SR_OV   11       // Optional
`define OR1200_SR_OVE  12       // Unused
`define OR1200_SR_OVE  12       // Optional
`define OR1200_SR_DSX  13       // Unused
`define OR1200_SR_DSX  13       // Unused
`define OR1200_SR_EPH  14
`define OR1200_SR_EPH  14
`define OR1200_SR_FO   15
`define OR1200_SR_FO   15
`define OR1200_SR_TED  16
`define OR1200_SR_TED  16
`define OR1200_SR_CID  31:28    // Unimplemented
`define OR1200_SR_CID  31:28    // Unimplemented
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`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets
`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries
`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
`define OR1200_DMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl.
`define OR1200_DMMUCFGR_TEIRI           1'b0    // TLB entry inv reg NOT impl.
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
`define OR1200_DMMUCFGR_RES1            20'h00000
`define OR1200_DMMUCFGR_RES1            20'h00000
`endif
`endif
 
 
// IMMUCFGR fields
// IMMUCFGR fields
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`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way
`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets
`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry
`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
`define OR1200_IMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl
`define OR1200_IMMUCFGR_TEIRI           1'b0    // TLB entry inv reg NOT impl
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
`define OR1200_IMMUCFGR_RES1            20'h00000
`define OR1200_IMMUCFGR_RES1            20'h00000
`endif
`endif
 
 
// DCCFGR fields
// DCCFGR fields

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