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[/] [minsoc/] [trunk/] [backend/] [ug257/] [minsoc_defines.v] - Diff between revs 149 and 158

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Rev 149 Rev 158
Line 96... Line 96...
 
 
//
//
// Connected modules
// Connected modules
//
//
`define UART
`define UART
 
//`define JSP
//`define ETHERNET
//`define ETHERNET
 
 
//
//
// Ethernet reset
// Ethernet reset
//
//
`define ETH_RESET       1'b0
`define ETH_RESET       1'b0
//`define ETH_RESET     1'b1
//`define ETH_RESET     1'b1
 
 
//
//
// Interrupts
 
//
 
`define APP_INT_RES1    1:0
 
`define APP_INT_UART    2
 
`define APP_INT_RES2    3
 
`define APP_INT_ETH     4
 
`define APP_INT_PS2     5
 
`define APP_INT_RES3    19:6
 
 
 
//
 
// Address map
 
//
 
`define APP_ADDR_DEC_W  8
 
`define APP_ADDR_SRAM   `APP_ADDR_DEC_W'h00
 
`define APP_ADDR_FLASH  `APP_ADDR_DEC_W'h04
 
`define APP_ADDR_DECP_W  4
 
`define APP_ADDR_PERIP  `APP_ADDR_DECP_W'h9
 
`define APP_ADDR_SPI    `APP_ADDR_DEC_W'h97
 
`define APP_ADDR_ETH    `APP_ADDR_DEC_W'h92
 
`define APP_ADDR_AUDIO  `APP_ADDR_DEC_W'h9d
 
`define APP_ADDR_UART   `APP_ADDR_DEC_W'h90
 
`define APP_ADDR_PS2    `APP_ADDR_DEC_W'h94
 
`define APP_ADDR_RES1   `APP_ADDR_DEC_W'h9e
 
`define APP_ADDR_RES2   `APP_ADDR_DEC_W'h9f
 
 
 
//
 
// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
//
//
`ifdef GENERIC_FPGA
`ifdef GENERIC_FPGA
    `undef FPGA_TAP
    `undef FPGA_TAP

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