| Line 58... |
Line 58... |
`ifdef UART
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`ifdef UART
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reg [40*8-1:0] line;
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reg [40*8-1:0] line;
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reg [12*8-1:0] hello;
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reg [12*8-1:0] hello;
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reg new_line;
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reg new_line;
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reg new_char;
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reg new_char;
|
|
reg flush_line;
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`endif
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`endif
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`ifdef ETHERNET
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`ifdef ETHERNET
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reg [7:0] eth_rx_data [0:1535]; //receive buffer ETH (max packet 1536)
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reg [7:0] eth_rx_data [0:1535]; //receive buffer ETH (max packet 1536)
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reg [7:0] eth_tx_data [0:1535]; //send buffer ETH (max packet 1536)
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reg [7:0] eth_tx_data [0:1535]; //send buffer ETH (max packet 1536)
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localparam ETH_HDR = 14;
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localparam ETH_HDR = 14;
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| Line 308... |
Line 309... |
uart_send(8'h41); //Character A
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uart_send(8'h41); //Character A
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@ (posedge new_char);
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@ (posedge new_char);
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if ( line[7:0] == "B" )
|
if ( line[7:0] == "B" )
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$display("UART interrupt working.");
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$display("UART interrupt working.");
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else
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else
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$display("UART interrupt failed.");
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$display("UART interrupt failed. B was expected, %c was received.", line[7:0]);
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uart_echo = 1'b1;
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uart_echo = 1'b1;
|
|
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if ( hello == "Hello World." )
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if ( hello == "Hello World." )
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$display("UART firmware test completed, behaving correctly.");
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$display("UART firmware test completed, behaving correctly.");
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else
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else
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| Line 345... |
Line 346... |
//
|
//
|
always begin
|
always begin
|
#((`CLK_PERIOD)/2) clock <= ~clock;
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#((`CLK_PERIOD)/2) clock <= ~clock;
|
end
|
end
|
|
|
`ifdef VCD_OUTPUT
|
`ifdef WAVEFORM_OUTPUT
|
initial begin
|
initial begin
|
$dumpfile("../results/minsoc_wave.vcd");
|
$dumpfile("../results/minsoc_wave.lxt2");
|
$dumpvars();
|
$dumpvars();
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end
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end
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`endif
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`endif
|
|
|
|
|
| Line 398... |
Line 399... |
// Something to trigger the task
|
// Something to trigger the task
|
initial
|
initial
|
begin
|
begin
|
new_line = 1'b0;
|
new_line = 1'b0;
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new_char = 1'b0;
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new_char = 1'b0;
|
|
flush_line = 1'b0;
|
end
|
end
|
|
|
always @ (posedge clock)
|
always @ (posedge clock)
|
if ( design_ready )
|
if ( design_ready )
|
uart_decoder;
|
uart_decoder;
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| Line 409... |
Line 411... |
task uart_decoder;
|
task uart_decoder;
|
integer i;
|
integer i;
|
reg [7:0] tx_byte;
|
reg [7:0] tx_byte;
|
begin
|
begin
|
new_char = 1'b0;
|
new_char = 1'b0;
|
|
new_line = 1'b0;
|
// Wait for start bit
|
// Wait for start bit
|
while (uart_stx == 1'b1)
|
while (uart_stx == 1'b1)
|
@(uart_stx);
|
@(uart_stx);
|
|
|
#(UART_TX_WAIT + (UART_TX_WAIT/2));
|
#(UART_TX_WAIT + (UART_TX_WAIT/2));
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| Line 429... |
Line 432... |
while (uart_stx == 1'b0)
|
while (uart_stx == 1'b0)
|
@(uart_stx);
|
@(uart_stx);
|
//$display("* USER UART returned to idle at time %d",$time);
|
//$display("* USER UART returned to idle at time %d",$time);
|
end
|
end
|
// display the char
|
// display the char
|
new_char = 1'b1;
|
|
if ( uart_echo )
|
if ( uart_echo )
|
$write("%c", tx_byte);
|
$write("%c", tx_byte);
|
if ( new_line )
|
if ( flush_line ) begin
|
line = "";
|
line = "";
|
if ( tx_byte == "\n" )
|
flush_line = 1'b0;
|
|
end
|
|
if ( tx_byte == "\n" ) begin
|
new_line = 1'b1;
|
new_line = 1'b1;
|
|
flush_line = 1'b1;
|
|
end
|
else begin
|
else begin
|
line = { line[39*8-1:0], tx_byte};
|
line = { line[39*8-1:0], tx_byte};
|
new_line = 1'b0;
|
new_char = 1'b1;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
//~UART Monitor
|
//~UART Monitor
|
`endif // !UART
|
`endif // !UART
|
