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[/] [minsoc/] [trunk/] [bench/] [verilog/] [minsoc_bench.v] - Diff between revs 141 and 149

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Rev 141 Rev 149
Line 58... Line 58...
`ifdef UART
`ifdef UART
reg [40*8-1:0] line;
reg [40*8-1:0] line;
reg [12*8-1:0] hello;
reg [12*8-1:0] hello;
reg new_line;
reg new_line;
reg new_char;
reg new_char;
 
reg flush_line;
`endif
`endif
`ifdef ETHERNET
`ifdef ETHERNET
reg [7:0] eth_rx_data [0:1535];            //receive buffer ETH (max packet 1536)
reg [7:0] eth_rx_data [0:1535];            //receive buffer ETH (max packet 1536)
reg [7:0] eth_tx_data [0:1535];     //send buffer ETH (max packet 1536)
reg [7:0] eth_tx_data [0:1535];     //send buffer ETH (max packet 1536)
localparam ETH_HDR = 14;
localparam ETH_HDR = 14;
Line 308... Line 309...
            uart_send(8'h41);       //Character A
            uart_send(8'h41);       //Character A
            @ (posedge new_char);
            @ (posedge new_char);
            if ( line[7:0] == "B" )
            if ( line[7:0] == "B" )
                $display("UART interrupt working.");
                $display("UART interrupt working.");
            else
            else
                $display("UART interrupt failed.");
                $display("UART interrupt failed. B was expected, %c was received.", line[7:0]);
            uart_echo = 1'b1;
            uart_echo = 1'b1;
 
 
            if ( hello == "Hello World." )
            if ( hello == "Hello World." )
                $display("UART firmware test completed, behaving correctly.");
                $display("UART firmware test completed, behaving correctly.");
            else
            else
Line 345... Line 346...
//
//
always begin
always begin
    #((`CLK_PERIOD)/2) clock <= ~clock;
    #((`CLK_PERIOD)/2) clock <= ~clock;
end
end
 
 
`ifdef VCD_OUTPUT
`ifdef WAVEFORM_OUTPUT
initial begin
initial begin
        $dumpfile("../results/minsoc_wave.vcd");
        $dumpfile("../results/minsoc_wave.lxt2");
        $dumpvars();
        $dumpvars();
end
end
`endif
`endif
 
 
 
 
Line 398... Line 399...
// Something to trigger the task
// Something to trigger the task
initial
initial
begin
begin
    new_line = 1'b0;
    new_line = 1'b0;
    new_char = 1'b0;
    new_char = 1'b0;
 
    flush_line = 1'b0;
end
end
 
 
always @ (posedge clock)
always @ (posedge clock)
    if ( design_ready )
    if ( design_ready )
        uart_decoder;
        uart_decoder;
Line 409... Line 411...
task uart_decoder;
task uart_decoder;
        integer i;
        integer i;
        reg [7:0] tx_byte;
        reg [7:0] tx_byte;
        begin
        begin
        new_char = 1'b0;
        new_char = 1'b0;
 
        new_line = 1'b0;
        // Wait for start bit
        // Wait for start bit
        while (uart_stx == 1'b1)
        while (uart_stx == 1'b1)
        @(uart_stx);
        @(uart_stx);
 
 
        #(UART_TX_WAIT + (UART_TX_WAIT/2));
        #(UART_TX_WAIT + (UART_TX_WAIT/2));
Line 429... Line 432...
            while (uart_stx == 1'b0)
            while (uart_stx == 1'b0)
            @(uart_stx);
            @(uart_stx);
            //$display("* USER UART returned to idle at time %d",$time);
            //$display("* USER UART returned to idle at time %d",$time);
        end
        end
        // display the char
        // display the char
        new_char = 1'b1;
 
        if ( uart_echo )
        if ( uart_echo )
            $write("%c", tx_byte);
            $write("%c", tx_byte);
        if ( new_line )
        if ( flush_line ) begin
            line = "";
            line = "";
        if ( tx_byte == "\n" )
            flush_line = 1'b0;
 
        end
 
        if ( tx_byte == "\n" ) begin
            new_line = 1'b1;
            new_line = 1'b1;
 
            flush_line = 1'b1;
 
        end
        else begin
        else begin
            line = { line[39*8-1:0], tx_byte};
            line = { line[39*8-1:0], tx_byte};
            new_line = 1'b0;
            new_char = 1'b1;
        end
        end
    end
    end
endtask
endtask
//~UART Monitor
//~UART Monitor
`endif // !UART
`endif // !UART

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