OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [bench/] [verilog/] [minsoc_memory_model.v] - Diff between revs 2 and 60

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 2 Rev 60
Line 50... Line 50...
// Revision 1.0 2009/08/18 15:15:00   fajardo
// Revision 1.0 2009/08/18 15:15:00   fajardo
// Created interface and tested
// Created interface and tested
//
//
 
 
 
 
module minsoc_onchip_ram_top (
module minsoc_memory_model (
  wb_clk_i, wb_rst_i,
  wb_clk_i, wb_rst_i,
 
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o
  wb_stb_i, wb_ack_o, wb_err_o
);
);

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.