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[/] [minsoc/] [trunk/] [bench/] [verilog/] [sim_lib/] [fpga_memory_primitives.v] - Diff between revs 10 and 17

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Rev 10 Rev 17
Line 645... Line 645...
        if (WE)
        if (WE)
                mem[{A4 , A3 , A2 , A1 , A0}] <= #1 D;
                mem[{A4 , A3 , A2 , A1 , A0}] <= #1 D;
 
 
endmodule
endmodule
//
//
// XILINX_RAM32X1D
// ~XILINX_RAM32X1D
//
//
 
 
 
 
//
//
// USE_RAM16X1D_FOR_RAM32X1D
// USE_RAM16X1D_FOR_RAM32X1D
Line 695... Line 695...
        if (WE)
        if (WE)
                mem[{A3 , A2 , A1 , A0}] <= #1 D;
                mem[{A3 , A2 , A1 , A0}] <= #1 D;
 
 
endmodule
endmodule
//
//
// USE_RAM16X1D_FOR_RAM32X1D
// ~USE_RAM16X1D_FOR_RAM32X1D
//
//
 
 
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