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[/] [minsoc/] [trunk/] [bench/] [verilog/] [vpi/] [dbg_comm_vpi.v] - Diff between revs 71 and 155

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Rev 71 Rev 155
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////       Raul Fajardo (rfajardo@gmail.com)                                      ////
////       Raul Fajardo (rfajardo@gmail.com)                                      ////
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
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//// Copyright (C) 2000-2008 Authors                              ////
//// Copyright (C) 2000-2011 Authors                              ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
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//
//
 
 
`include "timescale.v"
`include "timescale.v"
 
 
`define JP_PORT "4567"
`define JP_PORT "4567"
`define TIMEOUT_COUNT 6'd20  // 1/2 of a TCK clock will be this many SYS_CLK ticks.  Must be less than 6 bits. 
`define TIMEOUT_COUNT 6'd5  // 1/2 of a TCK clock will be this many SYS_CLK ticks.  Must be less than 6 bits. 
 
 
  module dbg_comm_vpi (
  module dbg_comm_vpi (
                       SYS_CLK,
                       SYS_CLK,
                       P_TMS,
                       P_TMS,
                       P_TCK,
                       P_TCK,

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