//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// dbg_comm_vpi.v ////
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//// dbg_comm_vpi.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// This file is part of the SoC/OpenRISC Development Interface ////
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//// http://www.opencores.org/cores/DebugInterface/ ////
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//// http://www.opencores.org/cores/DebugInterface/ ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// Gyorgy Jeney (nog@sdf.lonestar.net) ////
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//// Gyorgy Jeney (nog@sdf.lonestar.net) ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// Raul Fajardo (rfajardo@gmail.com) ////
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//// Raul Fajardo (rfajardo@gmail.com) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000-2008 Authors ////
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//// Copyright (C) 2000-2011 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: dbg_comm_vpi.v,v $
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// $Log: dbg_comm_vpi.v,v $
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// Revision 1.2.1 2009/09/08 14:57 rfajardo
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// Revision 1.2.1 2009/09/08 14:57 rfajardo
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// Changed clock and reset outputs to inputs for minsoc
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// Changed clock and reset outputs to inputs for minsoc
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//
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//
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// $Log: dbg_comm_vpi.v,v $
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// $Log: dbg_comm_vpi.v,v $
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// Revision 1.2 2009/05/17 20:55:57 Nathan
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// Revision 1.2 2009/05/17 20:55:57 Nathan
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// Changed email address to opencores.org
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// Changed email address to opencores.org
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//
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//
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// Revision 1.1 2008/07/26 17:33:20 Nathan
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// Revision 1.1 2008/07/26 17:33:20 Nathan
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// Added debug comm module for use with VPI / network communication.
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// Added debug comm module for use with VPI / network communication.
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//
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//
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// Revision 1.1 2002/03/28 19:59:54 lampret
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// Revision 1.1 2002/03/28 19:59:54 lampret
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// Added bench directory
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// Added bench directory
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//
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//
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// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
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// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
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// First import.
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// First import.
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//
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//
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// Revision 1.3 2001/09/24 14:06:13 mohor
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// Revision 1.3 2001/09/24 14:06:13 mohor
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// Changes connected to the OpenRISC access (SPR read, SPR write).
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// Changes connected to the OpenRISC access (SPR read, SPR write).
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//
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//
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// Revision 1.2 2001/09/20 10:10:30 mohor
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// Revision 1.2 2001/09/20 10:10:30 mohor
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// Working version. Few bugs fixed, comments added.
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// Working version. Few bugs fixed, comments added.
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//
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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// Initial official release.
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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`define JP_PORT "4567"
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`define JP_PORT "4567"
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`define TIMEOUT_COUNT 6'd20 // 1/2 of a TCK clock will be this many SYS_CLK ticks. Must be less than 6 bits.
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`define TIMEOUT_COUNT 6'd5 // 1/2 of a TCK clock will be this many SYS_CLK ticks. Must be less than 6 bits.
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module dbg_comm_vpi (
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module dbg_comm_vpi (
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SYS_CLK,
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SYS_CLK,
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P_TMS,
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P_TMS,
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P_TCK,
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P_TCK,
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P_TRST,
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P_TRST,
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P_TDI,
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P_TDI,
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P_TDO
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P_TDO
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);
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);
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//parameter Tp = 20;
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//parameter Tp = 20;
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input SYS_CLK;
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input SYS_CLK;
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output P_TMS;
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output P_TMS;
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output P_TCK;
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output P_TCK;
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output P_TRST;
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output P_TRST;
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output P_TDI;
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output P_TDI;
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input P_TDO;
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input P_TDO;
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reg [4:0] memory; // [0:0];
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reg [4:0] memory; // [0:0];
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wire P_TCK;
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wire P_TCK;
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wire P_TRST;
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wire P_TRST;
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wire P_TDI;
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wire P_TDI;
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wire P_TMS;
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wire P_TMS;
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wire P_TDO;
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wire P_TDO;
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reg [3:0] in_word_r;
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reg [3:0] in_word_r;
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reg [5:0] clk_count;
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reg [5:0] clk_count;
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// Handle commands from the upper level
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// Handle commands from the upper level
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initial
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initial
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begin
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begin
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in_word_r = 5'b0;
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in_word_r = 5'b0;
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memory = 5'b0;
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memory = 5'b0;
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$jp_init(`JP_PORT);
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$jp_init(`JP_PORT);
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#5500; // Wait until reset is complete
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#5500; // Wait until reset is complete
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while(1)
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while(1)
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begin
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begin
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#1;
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#1;
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$jp_in(memory); // This will not change memory[][] if no command has been sent from jp
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$jp_in(memory); // This will not change memory[][] if no command has been sent from jp
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if(memory[4]) // was memory[0][4]
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if(memory[4]) // was memory[0][4]
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begin
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begin
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in_word_r = memory[3:0];
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in_word_r = memory[3:0];
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memory = memory & 4'b1111;
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memory = memory & 4'b1111;
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clk_count = 6'b000000; // Reset the timeout clock in case jp wants to wait for a timeout / half TCK period
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clk_count = 6'b000000; // Reset the timeout clock in case jp wants to wait for a timeout / half TCK period
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end
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end
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end
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end
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end
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end
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// Send the output bit to the upper layer
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// Send the output bit to the upper layer
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always @ (P_TDO)
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always @ (P_TDO)
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begin
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begin
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$jp_out(P_TDO);
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$jp_out(P_TDO);
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end
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end
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assign P_TCK = in_word_r[0];
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assign P_TCK = in_word_r[0];
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assign P_TRST = in_word_r[1];
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assign P_TRST = in_word_r[1];
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assign P_TDI = in_word_r[2];
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assign P_TDI = in_word_r[2];
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assign P_TMS = in_word_r[3];
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assign P_TMS = in_word_r[3];
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// Send timeouts / wait periods to the upper layer
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// Send timeouts / wait periods to the upper layer
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always @ (posedge SYS_CLK)
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always @ (posedge SYS_CLK)
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begin
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begin
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if(clk_count < `TIMEOUT_COUNT) clk_count[5:0] = clk_count[5:0] + 1;
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if(clk_count < `TIMEOUT_COUNT) clk_count[5:0] = clk_count[5:0] + 1;
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else if(clk_count == `TIMEOUT_COUNT) begin
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else if(clk_count == `TIMEOUT_COUNT) begin
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$jp_wait_time();
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$jp_wait_time();
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clk_count[5:0] = clk_count[5:0] + 1;
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clk_count[5:0] = clk_count[5:0] + 1;
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end
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end
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// else it's already timed out, don't do anything
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// else it's already timed out, don't do anything
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end
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end
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endmodule
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endmodule
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