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[/] [minsoc/] [trunk/] [prj/] [Makefile] - Diff between revs 96 and 104

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Rev 96 Rev 104
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PROJECTS = minsoc_bench.prj minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj altera_virtual_jtag.prj
VERILOG_PROJECTS = minsoc_bench.prj minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj
 
VHDL_PROJECTS = altera_virtual_jtag.prj
 
 
 
PROJECTS = $(VERILOG_PROJECTS) $(VHDL_PROJECTS)
SRC_DIR = src
SRC_DIR = src
SCRIPTS_DIR = scripts
SCRIPTS_DIR = scripts
 
 
SIMULATION_DIR = sim
SIMULATION_DIR = sim
XILINX_DIR = xilinx
XILINX_DIR = xilinx
ALTERA_DIR = altera
ALTERA_DIR = altera
 
 
SIMULATION_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .src, $(basename $(PROJECTS))))
SIM_VERILOG_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .verilog, $(basename $(VERILOG_PROJECTS))))
 
SIM_VHDL_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .vhdl, $(basename $(VHDL_PROJECTS))))
XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS))))
XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS))))
ALTERA_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
ALTERA_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
 
 
all: $(SIMULATION_DIR)/minsoc.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_PRJ_FILES)
all: $(SIMULATION_DIR)/minsoc_verilog.src $(SIMULATION_DIR)/minsoc_vhdl.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_PRJ_FILES)
 
 
clean:
clean:
        rm -rf $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.prj
        rm -rf $(SIMULATION_DIR)/*.verilog $(SIMULATION_DIR)/*.vhdl $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.prj
 
 
$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj
$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj
        bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule
        bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule
 
 
$(XILINX_DIR)/minsoc_top.prj: $(SRC_DIR)/minsoc_top.prj
$(XILINX_DIR)/minsoc_top.prj: $(SRC_DIR)/minsoc_top.prj
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        bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@
        bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@
 
 
$(ALTERA_DIR)/%.prj: $(SRC_DIR)/%.prj
$(ALTERA_DIR)/%.prj: $(SRC_DIR)/%.prj
        bash $(SCRIPTS_DIR)/altprj.sh $^ $@
        bash $(SCRIPTS_DIR)/altprj.sh $^ $@
 
 
$(SIMULATION_DIR)/minsoc.src: $(SIMULATION_FILES)
$(SIMULATION_DIR)/minsoc_verilog.src: $(SIM_VERILOG_FILES)
        cat $(SIMULATION_FILES) > $(SIMULATION_DIR)/minsoc.src
        cat $(SIM_VERILOG_FILES) > $(SIMULATION_DIR)/minsoc_verilog.src
 
 
$(SIMULATION_DIR)/%.src: $(SRC_DIR)/%.prj
$(SIMULATION_DIR)/minsoc_vhdl.src: $(SIM_VHDL_FILES)
        bash $(SCRIPTS_DIR)/simprj.sh $^ $@
        cat $(SIM_VHDL_FILES) > $(SIMULATION_DIR)/minsoc_vhdl.src
 
 
 
$(SIMULATION_DIR)/%.verilog: $(SRC_DIR)/%.prj
 
        bash $(SCRIPTS_DIR)/simverilog.sh $^ $@
 
 
 
$(SIMULATION_DIR)/%.vhdl: $(SRC_DIR)/%.prj
 
        bash $(SCRIPTS_DIR)/simvhdl.sh $^ $@
 
 

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