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[/] [minsoc/] [trunk/] [prj/] [Makefile] - Diff between revs 104 and 141

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Rev 104 Rev 141
Line 9... Line 9...
XILINX_DIR = xilinx
XILINX_DIR = xilinx
ALTERA_DIR = altera
ALTERA_DIR = altera
 
 
SIM_VERILOG_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .verilog, $(basename $(VERILOG_PROJECTS))))
SIM_VERILOG_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .verilog, $(basename $(VERILOG_PROJECTS))))
SIM_VHDL_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .vhdl, $(basename $(VHDL_PROJECTS))))
SIM_VHDL_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .vhdl, $(basename $(VHDL_PROJECTS))))
 
 
XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS))))
XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS))))
ALTERA_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
 
 
 
all: $(SIMULATION_DIR)/minsoc_verilog.src $(SIMULATION_DIR)/minsoc_vhdl.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_PRJ_FILES)
ALTERA_VERILOG_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .vprj, $(basename $(VERILOG_PROJECTS))))
 
ALTERA_VHDL_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .vhdprj, $(basename $(VHDL_PROJECTS))))
 
 
 
all: $(SIMULATION_DIR)/minsoc_verilog.src $(SIMULATION_DIR)/minsoc_vhdl.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_VERILOG_PRJ_FILES) $(ALTERA_VHDL_PRJ_FILES)
 
 
clean:
clean:
        rm -rf $(SIMULATION_DIR)/*.verilog $(SIMULATION_DIR)/*.vhdl $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.prj
        rm -rf $(SIMULATION_DIR)/*.verilog $(SIMULATION_DIR)/*.vhdl $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.vprj $(ALTERA_DIR)/*.vhdprj
 
 
 
 
$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj
$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj
        bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule
        bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule
 
 
$(XILINX_DIR)/minsoc_top.prj: $(SRC_DIR)/minsoc_top.prj
$(XILINX_DIR)/minsoc_top.prj: $(SRC_DIR)/minsoc_top.prj
Line 30... Line 34...
        bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ $*.prj $*
        bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ $*.prj $*
 
 
$(XILINX_DIR)/%.prj: $(SRC_DIR)/%.prj
$(XILINX_DIR)/%.prj: $(SRC_DIR)/%.prj
        bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@
        bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@
 
 
$(ALTERA_DIR)/%.prj: $(SRC_DIR)/%.prj
 
        bash $(SCRIPTS_DIR)/altprj.sh $^ $@
$(ALTERA_DIR)/%.vprj: $(SRC_DIR)/%.prj
 
        bash $(SCRIPTS_DIR)/altvprj.sh $^ $@
 
 
 
$(ALTERA_DIR)/%.vhdprj: $(SRC_DIR)/%.prj
 
        bash $(SCRIPTS_DIR)/altvhdprj.sh $^ $@
 
 
 
 
$(SIMULATION_DIR)/minsoc_verilog.src: $(SIM_VERILOG_FILES)
$(SIMULATION_DIR)/minsoc_verilog.src: $(SIM_VERILOG_FILES)
        cat $(SIM_VERILOG_FILES) > $(SIMULATION_DIR)/minsoc_verilog.src
        cat $(SIM_VERILOG_FILES) > $(SIMULATION_DIR)/minsoc_verilog.src
 
 
$(SIMULATION_DIR)/minsoc_vhdl.src: $(SIM_VHDL_FILES)
$(SIMULATION_DIR)/minsoc_vhdl.src: $(SIM_VHDL_FILES)

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