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[/] [minsoc/] [trunk/] [prj/] [src/] [blackboxes/] [or1200_top.v] - Diff between revs 63 and 85

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`include "or1200_defines.v"
 
 
 
module or1200_top(
 
        // System
 
        clk_i, rst_i, pic_ints_i, clmode_i,
 
 
 
        // Instruction WISHBONE INTERFACE
 
        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
 
        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
 
`ifdef OR1200_WB_CAB
 
        iwb_cab_o,
 
`endif
 
`ifdef OR1200_WB_B3
 
        iwb_cti_o, iwb_bte_o,
 
`endif
 
        // Data WISHBONE INTERFACE
 
        dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
 
        dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
 
`ifdef OR1200_WB_CAB
 
        dwb_cab_o,
 
`endif
 
`ifdef OR1200_WB_B3
 
        dwb_cti_o, dwb_bte_o,
 
`endif
 
 
 
        // External Debug Interface
 
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
 
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
 
 
 
`ifdef OR1200_BIST
 
        // RAM BIST
 
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
 
`endif
 
        // Power Management
 
        pm_cpustall_i,
 
        pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
 
        pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
 
 
 
,sig_tick
 
 
 
);
 
 
 
parameter dw = `OR1200_OPERAND_WIDTH;
 
parameter aw = `OR1200_OPERAND_WIDTH;
 
parameter ppic_ints = `OR1200_PIC_INTS;
 
 
 
//
 
// I/O
 
//
 
 
 
//
 
// System
 
//
 
input                   clk_i;
 
input                   rst_i;
 
input   [1:0]            clmode_i;       // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
 
input   [ppic_ints-1:0]  pic_ints_i;
 
 
 
//
 
// Instruction WISHBONE interface
 
//
 
input                   iwb_clk_i;      // clock input
 
input                   iwb_rst_i;      // reset input
 
input                   iwb_ack_i;      // normal termination
 
input                   iwb_err_i;      // termination w/ error
 
input                   iwb_rty_i;      // termination w/ retry
 
input   [dw-1:0] iwb_dat_i;      // input data bus
 
output                  iwb_cyc_o;      // cycle valid output
 
output  [aw-1:0] iwb_adr_o;      // address bus outputs
 
output                  iwb_stb_o;      // strobe output
 
output                  iwb_we_o;       // indicates write transfer
 
output  [3:0]            iwb_sel_o;      // byte select outputs
 
output  [dw-1:0] iwb_dat_o;      // output data bus
 
`ifdef OR1200_WB_CAB
 
output                  iwb_cab_o;      // indicates consecutive address burst
 
`endif
 
`ifdef OR1200_WB_B3
 
output  [2:0]            iwb_cti_o;      // cycle type identifier
 
output  [1:0]            iwb_bte_o;      // burst type extension
 
`endif
 
 
 
//
 
// Data WISHBONE interface
 
//
 
input                   dwb_clk_i;      // clock input
 
input                   dwb_rst_i;      // reset input
 
input                   dwb_ack_i;      // normal termination
 
input                   dwb_err_i;      // termination w/ error
 
input                   dwb_rty_i;      // termination w/ retry
 
input   [dw-1:0] dwb_dat_i;      // input data bus
 
output                  dwb_cyc_o;      // cycle valid output
 
output  [aw-1:0] dwb_adr_o;      // address bus outputs
 
output                  dwb_stb_o;      // strobe output
 
output                  dwb_we_o;       // indicates write transfer
 
output  [3:0]            dwb_sel_o;      // byte select outputs
 
output  [dw-1:0] dwb_dat_o;      // output data bus
 
`ifdef OR1200_WB_CAB
 
output                  dwb_cab_o;      // indicates consecutive address burst
 
`endif
 
`ifdef OR1200_WB_B3
 
output  [2:0]            dwb_cti_o;      // cycle type identifier
 
output  [1:0]            dwb_bte_o;      // burst type extension
 
`endif
 
 
 
//
 
// External Debug Interface
 
//
 
input                   dbg_stall_i;    // External Stall Input
 
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
 
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
 
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
 
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
 
output                  dbg_bp_o;       // Breakpoint Output
 
input                   dbg_stb_i;      // External Address/Data Strobe
 
input                   dbg_we_i;       // External Write Enable
 
input   [aw-1:0] dbg_adr_i;      // External Address Input
 
input   [dw-1:0] dbg_dat_i;      // External Data Input
 
output  [dw-1:0] dbg_dat_o;      // External Data Output
 
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
 
 
 
`ifdef OR1200_BIST
 
//
 
// RAM BIST
 
//
 
input mbist_si_i;
 
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
 
output mbist_so_o;
 
`endif
 
 
 
//
 
// Power Management
 
//
 
input                   pm_cpustall_i;
 
output  [3:0]            pm_clksd_o;
 
output                  pm_dc_gate_o;
 
output                  pm_ic_gate_o;
 
output                  pm_dmmu_gate_o;
 
output                  pm_immu_gate_o;
 
output                  pm_tt_gate_o;
 
output                  pm_cpu_gate_o;
 
output                  pm_wakeup_o;
 
output                  pm_lvolt_o;
 
 
 
//
 
// CPU and TT
 
//
 
output          sig_tick; // jb
 
 
 
 
 
endmodule
 
 
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