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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_clock_manager.v] - Diff between revs 2 and 52

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Rev 2 Rev 52
Line 8... Line 8...
 
 
// 
// 
// Parameters 
// Parameters 
// 
// 
parameter    divisor = 5;
parameter    divisor = 5;
 
parameter    multiplier = 1;
 
 
input clk_i;
input clk_i;
output clk_o;
output clk_o;
 
 
`ifdef NO_CLOCK_DIVISION
`ifdef NO_CLOCK_DIVISION
Line 30... Line 31...
end
end
assign clk_o = clk_int;
assign clk_o = clk_int;
`elsif FPGA_CLOCK_DIVISION
`elsif FPGA_CLOCK_DIVISION
 
 
`ifdef ALTERA_FPGA
`ifdef ALTERA_FPGA
reg [31:0] clock_divisor;
minsoc_pll
reg clk_int;
#(
always @ (posedge clk_i)
   multiplier,
begin
   divisor
        clock_divisor <= clock_divisor + 1'b1;
)
        if ( clock_divisor >= divisor/2 - 1 ) begin
systemPll
                clk_int <= ~clk_int;
(
                clock_divisor <= 32'h0000_0000;
    .inclk0(clk_i),
        end
    .c0(clk_o)
end
);
assign clk_o = clk_int;
 
 
 
`elsif XILINX_FPGA
`elsif XILINX_FPGA
 
 
`ifdef SPARTAN2
`ifdef SPARTAN2
        `define MINSOC_DLL
        `define MINSOC_DLL

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