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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_clock_manager.v] - Diff between revs 2 and 52
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Rev 52 |
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Line 8... |
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//
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//
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// Parameters
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// Parameters
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//
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//
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parameter divisor = 5;
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parameter divisor = 5;
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parameter multiplier = 1;
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input clk_i;
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input clk_i;
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output clk_o;
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output clk_o;
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`ifdef NO_CLOCK_DIVISION
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`ifdef NO_CLOCK_DIVISION
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Line 31... |
end
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end
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assign clk_o = clk_int;
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assign clk_o = clk_int;
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`elsif FPGA_CLOCK_DIVISION
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`elsif FPGA_CLOCK_DIVISION
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`ifdef ALTERA_FPGA
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`ifdef ALTERA_FPGA
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reg [31:0] clock_divisor;
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minsoc_pll
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reg clk_int;
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#(
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always @ (posedge clk_i)
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multiplier,
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begin
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divisor
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clock_divisor <= clock_divisor + 1'b1;
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)
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if ( clock_divisor >= divisor/2 - 1 ) begin
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systemPll
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clk_int <= ~clk_int;
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(
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clock_divisor <= 32'h0000_0000;
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.inclk0(clk_i),
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end
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.c0(clk_o)
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end
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);
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assign clk_o = clk_int;
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`elsif XILINX_FPGA
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`elsif XILINX_FPGA
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`ifdef SPARTAN2
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`ifdef SPARTAN2
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`define MINSOC_DLL
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`define MINSOC_DLL
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