OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_onchip_ram.v] - Diff between revs 7 and 173

Show entire file | Details | Blame | View Log

Rev 7 Rev 173
Line 174... Line 174...
        `define MINSOC_XILINX_RAMB16
        `define MINSOC_XILINX_RAMB16
`elsif VIRTEX4
`elsif VIRTEX4
        `define MINSOC_XILINX_RAMB16
        `define MINSOC_XILINX_RAMB16
`elsif VIRTEX5
`elsif VIRTEX5
        `define MINSOC_XILINX_RAMB16
        `define MINSOC_XILINX_RAMB16
`endif  // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5
`elsif SPARTAN6
 
        `define MINSOC_XILINX_RAMB16
 
`endif  // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5/SPARTAN6
 
 
 
 
//
//
// Internal wires and registers
// Internal wires and registers
//
//

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.