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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_onchip_ram.v] - Diff between revs 7 and 173

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Rev 7 Rev 173
Line 174... Line 174...
        `define MINSOC_XILINX_RAMB16
        `define MINSOC_XILINX_RAMB16
`elsif VIRTEX4
`elsif VIRTEX4
        `define MINSOC_XILINX_RAMB16
        `define MINSOC_XILINX_RAMB16
`elsif VIRTEX5
`elsif VIRTEX5
        `define MINSOC_XILINX_RAMB16
        `define MINSOC_XILINX_RAMB16
`endif  // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5
`elsif SPARTAN6
 
        `define MINSOC_XILINX_RAMB16
 
`endif  // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5/SPARTAN6
 
 
 
 
//
//
// Internal wires and registers
// Internal wires and registers
//
//

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