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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_startup/] [spi_top.v] - Diff between revs 2 and 12

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Rev 2 Rev 12
Line 163... Line 163...
   assign rx_negedge = 1'b0;
   assign rx_negedge = 1'b0;
`endif
`endif
`ifdef SPI_CTRL_TX_NEGEDGE
`ifdef SPI_CTRL_TX_NEGEDGE
   assign tx_negedge = 1'b1;
   assign tx_negedge = 1'b1;
`else
`else
   assign tx_negedge = 1'b1;
   assign tx_negedge = 1'b0;
`endif
`endif
 
 
   assign ctrl = {ass,1'b0,lsb,tx_negedge,rx_negedge,go,1'b0,1'b0,char_len};
   assign ctrl = {ass,1'b0,lsb,tx_negedge,rx_negedge,go,1'b0,1'b0,char_len};
 
 
   // Slave select register
   // Slave select register

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