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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Diff between revs 7 and 14

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Rev 7 Rev 14
Line 755... Line 755...
        .int_o          ( pic_ints[`APP_INT_ETH] )
        .int_o          ( pic_ints[`APP_INT_ETH] )
);
);
`else
`else
assign wb_es_dat_o = 32'h0000_0000;
assign wb_es_dat_o = 32'h0000_0000;
assign wb_es_ack_o = 1'b0;
assign wb_es_ack_o = 1'b0;
 
assign wb_es_err_o = 1'b0;
 
 
assign wb_em_adr_o = 32'h0000_0000;
assign wb_em_adr_o = 32'h0000_0000;
assign wb_em_sel_o = 4'h0;
assign wb_em_sel_o = 4'h0;
assign wb_em_we_o = 1'b0;
assign wb_em_we_o = 1'b0;
assign wb_em_dat_o = 32'h0000_0000;
assign wb_em_dat_o = 32'h0000_0000;

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