OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Diff between revs 156 and 158

Show entire file | Details | Blame | View Log

Rev 156 Rev 158
Line 1... Line 1...
`include "minsoc_defines.v"
`include "minsoc_defines.v"
 
`include "interconnect_defines.v"
`include "or1200_defines.v"
`include "or1200_defines.v"
 
 
module minsoc_top (
module minsoc_top (
   clk,reset
   clk,reset
 
 
Line 114... Line 115...
wire                    wb_dm_cyc_o;
wire                    wb_dm_cyc_o;
wire                    wb_dm_ack_i;
wire                    wb_dm_ack_i;
wire                    wb_dm_err_i;
wire                    wb_dm_err_i;
 
 
//
//
 
// Debug core JSP slave i/f wires
 
//
 
wire    [31:0]   wb_jsp_dat_i;
 
wire    [31:0]   wb_jsp_dat_o;
 
wire    [31:0]   wb_jsp_adr_i;
 
wire    [3:0]    wb_jsp_sel_i;
 
wire                    wb_jsp_we_i;
 
wire                    wb_jsp_cyc_i;
 
wire                    wb_jsp_stb_i;
 
wire                    wb_jsp_ack_o;
 
wire                    wb_jsp_err_o;
 
 
 
//
// Debug <-> RISC wires
// Debug <-> RISC wires
//
//
wire    [3:0]            dbg_lss;
wire    [3:0]            dbg_lss;
wire    [1:0]            dbg_is;
wire    [1:0]            dbg_is;
wire    [10:0]           dbg_wp;
wire    [10:0]           dbg_wp;
Line 301... Line 315...
        .clk_i(clk),
        .clk_i(clk),
        .clk_o(wb_clk)
        .clk_o(wb_clk)
);
);
 
 
//
//
// Unused WISHBONE signals
 
//
 
assign wb_us_err_o = 1'b0;
 
assign wb_fs_err_o = 1'b0;
 
assign wb_sp_err_o = 1'b0;
 
 
 
//
 
// Unused interrupts
// Unused interrupts
//
//
assign pic_ints[`APP_INT_RES1] = 'b0;
assign pic_ints[`APP_INT_RES1] = 'b0;
assign pic_ints[`APP_INT_RES2] = 'b0;
assign pic_ints[`APP_INT_RES2] = 'b0;
assign pic_ints[`APP_INT_RES3] = 'b0;
assign pic_ints[`APP_INT_RES3] = 'b0;
Line 443... Line 450...
      .cpu0_bp_i   ( (dbg_bp | (| dbg_wp[10:0])) ),
      .cpu0_bp_i   ( (dbg_bp | (| dbg_wp[10:0])) ),
      .cpu0_stall_o( dbg_stall ),
      .cpu0_stall_o( dbg_stall ),
      .cpu0_stb_o  ( dbg_stb ),
      .cpu0_stb_o  ( dbg_stb ),
      .cpu0_we_o   ( dbg_we ),
      .cpu0_we_o   ( dbg_we ),
      .cpu0_ack_i  ( dbg_ack ),
      .cpu0_ack_i  ( dbg_ack ),
      .cpu0_rst_o  ( )
      .cpu0_rst_o  ( ),
 
 
 
      // WISHBONE slave interface (JTAG UART)
 
`ifdef JSP
 
      .wb_jsp_adr_i     ( wb_jsp_adr_i[31:0] ),
 
      .wb_jsp_dat_i     ( wb_jsp_dat_i[31:0] ),
 
      .wb_jsp_dat_o     ( wb_jsp_dat_o[31:0] ),
 
      .wb_jsp_we_i      ( wb_jsp_we_i ),
 
      .wb_jsp_stb_i     ( wb_jsp_stb_i ),
 
      .wb_jsp_cyc_i     ( wb_jsp_cyc_i ),
 
      .wb_jsp_ack_o     ( wb_jsp_ack_o ),
 
      .wb_jsp_sel_i     ( wb_jsp_sel_i[3:0] ),
 
      .wb_jsp_cab_i     ( 1'b0 ),
 
      .wb_jsp_cti_i     ( 3'b0 ),
 
      .wb_jsp_bte_i     ( 2'b0 ),
 
 
 
       // Interrupt request
 
      .int_o ( pic_ints[`APP_INT_JSP] )
 
`else
 
      .wb_jsp_adr_i     ( 32'h0000_0000 ),
 
      .wb_jsp_dat_i     ( 32'h0000_0000 ),
 
      .wb_jsp_dat_o     ( ),
 
      .wb_jsp_we_i      ( 1'b0 ),
 
      .wb_jsp_stb_i     ( 1'b0 ),
 
      .wb_jsp_cyc_i     ( 1'b0 ),
 
      .wb_jsp_ack_o     ( ),
 
      .wb_jsp_sel_i     ( 4'h0 ),
 
      .wb_jsp_cab_i     ( 1'b0 ),
 
      .wb_jsp_cti_i     ( 3'b0 ),
 
      .wb_jsp_bte_i     ( 2'b0 ),
 
 
 
       // Interrupt request
 
      .int_o ( )
 
`endif
);
);
 
 
 
`ifdef JSP
 
    assign wb_jsp_err_o = 1'b0;
 
`else
 
        assign wb_jsp_dat_o = 32'h0000_0000;
 
        assign wb_jsp_ack_o = 1'b0;
 
    assign wb_jsp_err_o = 1'b1;
 
        assign pic_ints[`APP_INT_JSP] = 1'b0;
 
`endif
 
 
 
 
//
//
// JTAG TAP controller instantiation
// JTAG TAP controller instantiation
//
//
`ifdef GENERIC_TAP
`ifdef GENERIC_TAP
tap_top tap_top(
tap_top tap_top(
Line 629... Line 678...
   .mosi_pad_o(spi_flash_mosi),
   .mosi_pad_o(spi_flash_mosi),
   .miso_pad_i(spi_flash_miso),
   .miso_pad_i(spi_flash_miso),
   .sclk_pad_o(spi_flash_sclk),
   .sclk_pad_o(spi_flash_sclk),
   .ss_pad_o(spi_flash_ss)
   .ss_pad_o(spi_flash_ss)
);
);
 
 
 
assign wb_fs_err_o = 1'b0;
 
assign wb_sp_err_o = 1'b0;
 
 
`else
`else
assign wb_fs_dat_o = 32'h0000_0000;
assign wb_fs_dat_o = 32'h0000_0000;
assign wb_fs_ack_o = 1'b0;
assign wb_fs_ack_o = 1'b0;
 
assign wb_fs_err_o = 1'b1;
assign wb_sp_dat_o = 32'h0000_0000;
assign wb_sp_dat_o = 32'h0000_0000;
assign wb_sp_ack_o = 1'b0;
assign wb_sp_ack_o = 1'b0;
 
assign wb_sp_err_o = 1'b1;
`endif
`endif
 
 
//
//
// Instantiation of the SRAM controller
// Instantiation of the SRAM controller
//
//
Line 701... Line 756...
        .dtr_pad_o      ( ),
        .dtr_pad_o      ( ),
        .dsr_pad_i      ( 1'b0 ),
        .dsr_pad_i      ( 1'b0 ),
        .ri_pad_i       ( 1'b0 ),
        .ri_pad_i       ( 1'b0 ),
        .dcd_pad_i      ( 1'b0 )
        .dcd_pad_i      ( 1'b0 )
);
);
 
 
 
assign wb_us_err_o = 1'b0;
`else
`else
assign wb_us_dat_o = 32'h0000_0000;
assign wb_us_dat_o = 32'h0000_0000;
assign wb_us_ack_o = 1'b0;
assign wb_us_ack_o = 1'b0;
 
assign wb_us_err_o = 1'b1;
 
 
assign pic_ints[`APP_INT_UART] = 1'b0;
assign pic_ints[`APP_INT_UART] = 1'b0;
`endif
`endif
 
 
//
//
Line 766... Line 824...
        .int_o          ( pic_ints[`APP_INT_ETH] )
        .int_o          ( pic_ints[`APP_INT_ETH] )
);
);
`else
`else
assign wb_es_dat_o = 32'h0000_0000;
assign wb_es_dat_o = 32'h0000_0000;
assign wb_es_ack_o = 1'b0;
assign wb_es_ack_o = 1'b0;
assign wb_es_err_o = 1'b0;
assign wb_es_err_o = 1'b1;
 
 
assign wb_em_adr_o = 32'h0000_0000;
assign wb_em_adr_o = 32'h0000_0000;
assign wb_em_sel_o = 4'h0;
assign wb_em_sel_o = 4'h0;
assign wb_em_we_o = 1'b0;
assign wb_em_we_o = 1'b0;
assign wb_em_dat_o = 32'h0000_0000;
assign wb_em_dat_o = 32'h0000_0000;
Line 793... Line 851...
         `APP_ADDR_SPI,
         `APP_ADDR_SPI,
         `APP_ADDR_ETH,
         `APP_ADDR_ETH,
         `APP_ADDR_AUDIO,
         `APP_ADDR_AUDIO,
         `APP_ADDR_UART,
         `APP_ADDR_UART,
         `APP_ADDR_PS2,
         `APP_ADDR_PS2,
         `APP_ADDR_RES1,
         `APP_ADDR_JSP,
         `APP_ADDR_RES2
         `APP_ADDR_RES2
        ) tc_top (
        ) tc_top (
 
 
        // WISHBONE common
        // WISHBONE common
        .wb_clk_i       ( wb_clk ),
        .wb_clk_i       ( wb_clk ),
Line 967... Line 1025...
        .t6_wb_dat_i    ( 32'h0000_0000 ),
        .t6_wb_dat_i    ( 32'h0000_0000 ),
        .t6_wb_ack_i    ( 1'b0 ),
        .t6_wb_ack_i    ( 1'b0 ),
        .t6_wb_err_i    ( 1'b1 ),
        .t6_wb_err_i    ( 1'b1 ),
 
 
        // WISHBONE Target 7
        // WISHBONE Target 7
        .t7_wb_cyc_o    ( ),
    .t7_wb_cyc_o        ( wb_jsp_cyc_i ),
        .t7_wb_stb_o    ( ),
    .t7_wb_stb_o        ( wb_jsp_stb_i ),
        .t7_wb_adr_o    ( ),
    .t7_wb_adr_o        ( wb_jsp_adr_i ),
        .t7_wb_sel_o    ( ),
    .t7_wb_sel_o        ( wb_jsp_sel_i ),
        .t7_wb_we_o     ( ),
    .t7_wb_we_o ( wb_jsp_we_i  ),
        .t7_wb_dat_o    ( ),
    .t7_wb_dat_o        ( wb_jsp_dat_i ),
        .t7_wb_dat_i    ( 32'h0000_0000 ),
    .t7_wb_dat_i        ( wb_jsp_dat_o ),
        .t7_wb_ack_i    ( 1'b0 ),
    .t7_wb_ack_i        ( wb_jsp_ack_o ),
        .t7_wb_err_i    ( 1'b1 ),
    .t7_wb_err_i        ( wb_jsp_err_o ),
 
 
        // WISHBONE Target 8
        // WISHBONE Target 8
        .t8_wb_cyc_o    ( ),
        .t8_wb_cyc_o    ( ),
        .t8_wb_stb_o    ( ),
        .t8_wb_stb_o    ( ),
        .t8_wb_adr_o    ( ),
        .t8_wb_adr_o    ( ),

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.