OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Diff between revs 16 and 17

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 16 Rev 17
Line 695... Line 695...
        .dcd_pad_i      ( 1'b0 )
        .dcd_pad_i      ( 1'b0 )
);
);
`else
`else
assign wb_us_dat_o = 32'h0000_0000;
assign wb_us_dat_o = 32'h0000_0000;
assign wb_us_ack_o = 1'b0;
assign wb_us_ack_o = 1'b0;
 
 
assign pic_ints[`APP_INT_UART] = 1'b0;
assign pic_ints[`APP_INT_UART] = 1'b0;
`endif
`endif
 
 
//
//
// Instantiation of the Ethernet 10/100 MAC
// Instantiation of the Ethernet 10/100 MAC
Line 764... Line 765...
assign wb_em_sel_o = 4'h0;
assign wb_em_sel_o = 4'h0;
assign wb_em_we_o = 1'b0;
assign wb_em_we_o = 1'b0;
assign wb_em_dat_o = 32'h0000_0000;
assign wb_em_dat_o = 32'h0000_0000;
assign wb_em_cyc_o = 1'b0;
assign wb_em_cyc_o = 1'b0;
assign wb_em_stb_o = 1'b0;
assign wb_em_stb_o = 1'b0;
 
 
assign pic_ints[`APP_INT_ETH] = 1'b0;
assign pic_ints[`APP_INT_ETH] = 1'b0;
`endif
`endif
 
 
//
//
// Instantiation of the Traffic COP
// Instantiation of the Traffic COP

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.