OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Diff between revs 20 and 26

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 20 Rev 26
Line 482... Line 482...
);
);
`elsif FPGA_TAP
`elsif FPGA_TAP
`ifdef ALTERA_FPGA
`ifdef ALTERA_FPGA
altera_virtual_jtag tap_top(
altera_virtual_jtag tap_top(
        .tck_o(jtag_tck),
        .tck_o(jtag_tck),
        .debug_tdo_o(debug_tdo),
        .debug_tdo_i(debug_tdo),
        .tdi_o(debug_tdi),
        .tdi_o(debug_tdi),
        .test_logic_reset_o(test_logic_reset),
        .test_logic_reset_o(test_logic_reset),
        .run_test_idle_o(),
        .run_test_idle_o(),
        .shift_dr_o(shift_dr),
        .shift_dr_o(shift_dr),
        .capture_dr_o(capture_dr),
        .capture_dr_o(capture_dr),

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.