OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Diff between revs 26 and 31

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 26 Rev 31
Line 162... Line 162...
wire                    wb_rdm_stb_o;
wire                    wb_rdm_stb_o;
 
 
//
//
// RISC misc
// RISC misc
//
//
wire    [19:0]           pic_ints;
wire    [`OR1200_PIC_INTS-1:0]           pic_ints;
 
 
//
//
// Flash controller slave i/f wires
// Flash controller slave i/f wires
//
//
wire    [31:0]           wb_fs_dat_i;
wire    [31:0]           wb_fs_dat_i;

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.