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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Diff between revs 26 and 31

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Rev 26 Rev 31
Line 162... Line 162...
wire                    wb_rdm_stb_o;
wire                    wb_rdm_stb_o;
 
 
//
//
// RISC misc
// RISC misc
//
//
wire    [19:0]           pic_ints;
wire    [`OR1200_PIC_INTS-1:0]           pic_ints;
 
 
//
//
// Flash controller slave i/f wires
// Flash controller slave i/f wires
//
//
wire    [31:0]           wb_fs_dat_i;
wire    [31:0]           wb_fs_dat_i;

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