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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Diff between revs 56 and 60

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Rev 56 Rev 60
Line 638... Line 638...
`endif
`endif
 
 
//
//
// Instantiation of the SRAM controller
// Instantiation of the SRAM controller
//
//
 
`ifdef MEMORY_MODEL
 
minsoc_memory_model #
 
`else
minsoc_onchip_ram_top #
minsoc_onchip_ram_top #
 
`endif
(
(
    .adr_width(`MEMORY_ADR_WIDTH)     //16 blocks of 2048 bytes memory 32768
    .adr_width(`MEMORY_ADR_WIDTH)     //16 blocks of 2048 bytes memory 32768
)
)
onchip_ram_top (
onchip_ram_top (
 
 

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