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Line 1... Line 1...
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////  OR1K test application for XESS XSV board, Top Level         ////
 
////                                                              ////
 
////  This file is part of the OR1K test application              ////
 
////  http://www.opencores.org/cores/or1k/                        ////
 
////                                                              ////
 
////  Description                                                 ////
 
////  Top level instantiating all the blocks.                     ////
 
////                                                              ////
 
////  To Do:                                                      ////
 
////   - nothing really                                           ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////      - Damjan Lampret, lampret@opencores.org                 ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
//// Copyright (C) 2001 Authors                                   ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
////                                                              ////
 
//// This source file is free software; you can redistribute it   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// later version.                                               ////
 
////                                                              ////
 
//// This source is distributed in the hope that it will be       ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// details.                                                     ////
 
////                                                              ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//
 
// CVS Revision History
 
//
 
// $Log: xsv_fpga_top.v,v $
 
// Revision 1.10  2004/04/05 08:44:35  lampret
 
// Merged branch_qmem into main tree.
 
//
 
// Revision 1.8  2003/04/07 21:05:58  lampret
 
// WB = 1/2 RISC clock test code enabled.
 
//
 
// Revision 1.7  2003/04/07 01:28:17  lampret
 
// Adding OR1200_CLMODE_1TO2 test code.
 
//
 
// Revision 1.6  2002/08/12 05:35:12  lampret
 
// rty_i are unused - tied to zero.
 
//
 
// Revision 1.5  2002/03/29 20:58:51  lampret
 
// Changed hardcoded address for fake MC to use a define.
 
//
 
// Revision 1.4  2002/03/29 16:30:47  lampret
 
// Fixed port names that changed.
 
//
 
// Revision 1.3  2002/03/29 15:50:03  lampret
 
// Added response from memory controller (addr 0x60000000)
 
//
 
// Revision 1.2  2002/03/21 17:39:16  lampret
 
// Fixed some typos
 
//
 
//
 
 
 
`include "minsoc_defines.v"
`include "minsoc_defines.v"
`include "or1200_defines.v"
`include "or1200_defines.v"
 
 
module minsoc_top (
module minsoc_top (
   clk,reset
   clk,reset
Line 162... Line 90...
assign jtag_gnd = 1'b0;
assign jtag_gnd = 1'b0;
`endif
`endif
 
 
wire rstn;
wire rstn;
 
 
 
`ifdef POSITIVE_RESET
assign rstn = ~reset;
assign rstn = ~reset;
 
`elsif NEGATIVE_RESET
 
assign rstn = reset;
 
`endif
 
 
//
//
// Internal wires
// Internal wires
//
//
 
 
Line 178... Line 110...
wire    [31:0]           wb_dm_dat_o;
wire    [31:0]           wb_dm_dat_o;
wire    [3:0]            wb_dm_sel_o;
wire    [3:0]            wb_dm_sel_o;
wire                    wb_dm_we_o;
wire                    wb_dm_we_o;
wire                    wb_dm_stb_o;
wire                    wb_dm_stb_o;
wire                    wb_dm_cyc_o;
wire                    wb_dm_cyc_o;
wire                    wb_dm_cab_o;
 
wire                    wb_dm_ack_i;
wire                    wb_dm_ack_i;
wire                    wb_dm_err_i;
wire                    wb_dm_err_i;
 
 
//
//
// Debug <-> RISC wires
// Debug <-> RISC wires
Line 210... Line 141...
wire                    wb_rim_ack_i;
wire                    wb_rim_ack_i;
wire                    wb_rim_err_i;
wire                    wb_rim_err_i;
wire                    wb_rim_rty_i = 1'b0;
wire                    wb_rim_rty_i = 1'b0;
wire                    wb_rim_we_o;
wire                    wb_rim_we_o;
wire                    wb_rim_stb_o;
wire                    wb_rim_stb_o;
wire                    wb_rim_cab_o;
 
wire    [31:0]           wb_rif_dat_i;
wire    [31:0]           wb_rif_dat_i;
wire                    wb_rif_ack_i;
wire                    wb_rif_ack_i;
 
 
//
//
// RISC data master i/f wires
// RISC data master i/f wires
Line 227... Line 157...
wire                    wb_rdm_ack_i;
wire                    wb_rdm_ack_i;
wire                    wb_rdm_err_i;
wire                    wb_rdm_err_i;
wire                    wb_rdm_rty_i = 1'b0;
wire                    wb_rdm_rty_i = 1'b0;
wire                    wb_rdm_we_o;
wire                    wb_rdm_we_o;
wire                    wb_rdm_stb_o;
wire                    wb_rdm_stb_o;
wire                    wb_rdm_cab_o;
 
 
 
//
//
// RISC misc
// RISC misc
//
//
wire    [19:0]           pic_ints;
wire    [19:0]           pic_ints;
Line 291... Line 220...
wire    [31:0]           wb_em_dat_o;
wire    [31:0]           wb_em_dat_o;
wire    [3:0]            wb_em_sel_o;
wire    [3:0]            wb_em_sel_o;
wire                    wb_em_we_o;
wire                    wb_em_we_o;
wire                    wb_em_stb_o;
wire                    wb_em_stb_o;
wire                    wb_em_cyc_o;
wire                    wb_em_cyc_o;
wire                    wb_em_cab_o;
 
wire                    wb_em_ack_i;
wire                    wb_em_ack_i;
wire                    wb_em_err_i;
wire                    wb_em_err_i;
 
 
//
//
// Ethernet core slave i/f wires
// Ethernet core slave i/f wires
Line 342... Line 270...
reg                     wb_rst;
reg                     wb_rst;
 
 
//
//
// Global clock
// Global clock
//
//
`ifdef OR1200_CLMODE_1TO2
 
reg                     wb_clk;
 
`else
 
wire                    wb_clk;
wire                    wb_clk;
`endif
 
 
 
//
//
// Reset debounce
// Reset debounce
//
//
always @(posedge wb_clk or negedge rstn)
always @(posedge wb_clk or negedge rstn)
Line 364... Line 288...
//
//
always @(posedge wb_clk)
always @(posedge wb_clk)
        wb_rst <= #1 rst_r;
        wb_rst <= #1 rst_r;
 
 
//
//
// This is purely for testing 1/2 WB clock
// Clock Divider
// This should never be used when implementing in
 
// an FPGA. It is used only for simulation regressions.
 
//
//
`ifdef OR1200_CLMODE_1TO2
 
initial wb_clk = 0;
 
always @(posedge clk)
 
        wb_clk = ~wb_clk;
 
`else
 
minsoc_clock_manager #
minsoc_clock_manager #
(
(
   .divisor(`CLOCK_DIVISOR)
   .divisor(`CLOCK_DIVISOR)
)
)
clk_adjust (
clk_adjust (
        .clk_i(clk),
        .clk_i(clk),
        .clk_o(wb_clk)
        .clk_o(wb_clk)
);
);
`endif // OR1200_CLMODE_1TO2
 
 
 
//
//
// Unused WISHBONE signals
// Unused WISHBONE signals
//
//
assign wb_us_err_o = 1'b0;
assign wb_us_err_o = 1'b0;
assign wb_em_cab_o = 1'b0;
 
assign wb_fs_err_o = 1'b0;
assign wb_fs_err_o = 1'b0;
assign wb_sp_err_o = 1'b0;
assign wb_sp_err_o = 1'b0;
 
 
//
//
// Unused interrupts
// Unused interrupts
Line 508... Line 423...
      .wb_dat_o  ( wb_dm_dat_o ),
      .wb_dat_o  ( wb_dm_dat_o ),
      .wb_sel_o  ( wb_dm_sel_o ),
      .wb_sel_o  ( wb_dm_sel_o ),
      .wb_we_o   ( wb_dm_we_o  ),
      .wb_we_o   ( wb_dm_we_o  ),
      .wb_stb_o  ( wb_dm_stb_o ),
      .wb_stb_o  ( wb_dm_stb_o ),
      .wb_cyc_o  ( wb_dm_cyc_o ),
      .wb_cyc_o  ( wb_dm_cyc_o ),
      .wb_cab_o  ( wb_dm_cab_o ),
 
      .wb_ack_i  ( wb_dm_ack_i ),
      .wb_ack_i  ( wb_dm_ack_i ),
      .wb_err_i  ( wb_dm_err_i ),
      .wb_err_i  ( wb_dm_err_i ),
      .wb_cti_o  ( ),
      .wb_cti_o  ( ),
      .wb_bte_o  ( ),
      .wb_bte_o  ( ),
 
 
Line 627... Line 541...
        .iwb_ack_i      ( wb_rif_ack_i ),
        .iwb_ack_i      ( wb_rif_ack_i ),
        .iwb_err_i      ( wb_rim_err_i ),
        .iwb_err_i      ( wb_rim_err_i ),
        .iwb_rty_i      ( wb_rim_rty_i ),
        .iwb_rty_i      ( wb_rim_rty_i ),
        .iwb_we_o       ( wb_rim_we_o  ),
        .iwb_we_o       ( wb_rim_we_o  ),
        .iwb_stb_o      ( wb_rim_stb_o ),
        .iwb_stb_o      ( wb_rim_stb_o ),
        .iwb_cab_o      ( wb_rim_cab_o ),
 
 
 
        // WISHBONE Data Master
        // WISHBONE Data Master
        .dwb_clk_i      ( wb_clk ),
        .dwb_clk_i      ( wb_clk ),
        .dwb_rst_i      ( wb_rst ),
        .dwb_rst_i      ( wb_rst ),
        .dwb_cyc_o      ( wb_rdm_cyc_o ),
        .dwb_cyc_o      ( wb_rdm_cyc_o ),
Line 642... Line 555...
        .dwb_ack_i      ( wb_rdm_ack_i ),
        .dwb_ack_i      ( wb_rdm_ack_i ),
        .dwb_err_i      ( wb_rdm_err_i ),
        .dwb_err_i      ( wb_rdm_err_i ),
        .dwb_rty_i      ( wb_rdm_rty_i ),
        .dwb_rty_i      ( wb_rdm_rty_i ),
        .dwb_we_o       ( wb_rdm_we_o  ),
        .dwb_we_o       ( wb_rdm_we_o  ),
        .dwb_stb_o      ( wb_rdm_stb_o ),
        .dwb_stb_o      ( wb_rdm_stb_o ),
        .dwb_cab_o      ( wb_rdm_cab_o ),
 
 
 
        // Debug
        // Debug
        .dbg_stall_i    ( dbg_stall ),
        .dbg_stall_i    ( dbg_stall ),
        .dbg_dat_i      ( dbg_dat_dbg ),
        .dbg_dat_i      ( dbg_dat_dbg ),
        .dbg_adr_i      ( dbg_adr ),
        .dbg_adr_i      ( dbg_adr ),
Line 878... Line 790...
        .wb_rst_i       ( wb_rst ),
        .wb_rst_i       ( wb_rst ),
 
 
        // WISHBONE Initiator 0
        // WISHBONE Initiator 0
        .i0_wb_cyc_i    ( 1'b0 ),
        .i0_wb_cyc_i    ( 1'b0 ),
        .i0_wb_stb_i    ( 1'b0 ),
        .i0_wb_stb_i    ( 1'b0 ),
        .i0_wb_cab_i    ( 1'b0 ),
 
        .i0_wb_adr_i    ( 32'h0000_0000 ),
        .i0_wb_adr_i    ( 32'h0000_0000 ),
        .i0_wb_sel_i    ( 4'b0000 ),
        .i0_wb_sel_i    ( 4'b0000 ),
        .i0_wb_we_i     ( 1'b0 ),
        .i0_wb_we_i     ( 1'b0 ),
        .i0_wb_dat_i    ( 32'h0000_0000 ),
        .i0_wb_dat_i    ( 32'h0000_0000 ),
        .i0_wb_dat_o    ( ),
        .i0_wb_dat_o    ( ),
Line 890... Line 801...
        .i0_wb_err_o    ( ),
        .i0_wb_err_o    ( ),
 
 
        // WISHBONE Initiator 1
        // WISHBONE Initiator 1
        .i1_wb_cyc_i    ( wb_em_cyc_o ),
        .i1_wb_cyc_i    ( wb_em_cyc_o ),
        .i1_wb_stb_i    ( wb_em_stb_o ),
        .i1_wb_stb_i    ( wb_em_stb_o ),
        .i1_wb_cab_i    ( wb_em_cab_o ),
 
        .i1_wb_adr_i    ( wb_em_adr_o ),
        .i1_wb_adr_i    ( wb_em_adr_o ),
        .i1_wb_sel_i    ( wb_em_sel_o ),
        .i1_wb_sel_i    ( wb_em_sel_o ),
        .i1_wb_we_i     ( wb_em_we_o  ),
        .i1_wb_we_i     ( wb_em_we_o  ),
        .i1_wb_dat_i    ( wb_em_dat_o ),
        .i1_wb_dat_i    ( wb_em_dat_o ),
        .i1_wb_dat_o    ( wb_em_dat_i ),
        .i1_wb_dat_o    ( wb_em_dat_i ),
Line 902... Line 812...
        .i1_wb_err_o    ( wb_em_err_i ),
        .i1_wb_err_o    ( wb_em_err_i ),
 
 
        // WISHBONE Initiator 2
        // WISHBONE Initiator 2
        .i2_wb_cyc_i    ( 1'b0 ),
        .i2_wb_cyc_i    ( 1'b0 ),
        .i2_wb_stb_i    ( 1'b0 ),
        .i2_wb_stb_i    ( 1'b0 ),
        .i2_wb_cab_i    ( 1'b0 ),
 
        .i2_wb_adr_i    ( 32'h0000_0000 ),
        .i2_wb_adr_i    ( 32'h0000_0000 ),
        .i2_wb_sel_i    ( 4'b0000 ),
        .i2_wb_sel_i    ( 4'b0000 ),
        .i2_wb_we_i     ( 1'b0 ),
        .i2_wb_we_i     ( 1'b0 ),
        .i2_wb_dat_i    ( 32'h0000_0000 ),
        .i2_wb_dat_i    ( 32'h0000_0000 ),
        .i2_wb_dat_o    ( ),
        .i2_wb_dat_o    ( ),
Line 914... Line 823...
        .i2_wb_err_o    ( ),
        .i2_wb_err_o    ( ),
 
 
        // WISHBONE Initiator 3
        // WISHBONE Initiator 3
        .i3_wb_cyc_i    ( wb_dm_cyc_o ),
        .i3_wb_cyc_i    ( wb_dm_cyc_o ),
        .i3_wb_stb_i    ( wb_dm_stb_o ),
        .i3_wb_stb_i    ( wb_dm_stb_o ),
        .i3_wb_cab_i    ( wb_dm_cab_o ),
 
        .i3_wb_adr_i    ( wb_dm_adr_o ),
        .i3_wb_adr_i    ( wb_dm_adr_o ),
        .i3_wb_sel_i    ( wb_dm_sel_o ),
        .i3_wb_sel_i    ( wb_dm_sel_o ),
        .i3_wb_we_i     ( wb_dm_we_o  ),
        .i3_wb_we_i     ( wb_dm_we_o  ),
        .i3_wb_dat_i    ( wb_dm_dat_o ),
        .i3_wb_dat_i    ( wb_dm_dat_o ),
        .i3_wb_dat_o    ( wb_dm_dat_i ),
        .i3_wb_dat_o    ( wb_dm_dat_i ),
Line 926... Line 834...
        .i3_wb_err_o    ( wb_dm_err_i ),
        .i3_wb_err_o    ( wb_dm_err_i ),
 
 
        // WISHBONE Initiator 4
        // WISHBONE Initiator 4
        .i4_wb_cyc_i    ( wb_rdm_cyc_o ),
        .i4_wb_cyc_i    ( wb_rdm_cyc_o ),
        .i4_wb_stb_i    ( wb_rdm_stb_o ),
        .i4_wb_stb_i    ( wb_rdm_stb_o ),
        .i4_wb_cab_i    ( wb_rdm_cab_o ),
 
        .i4_wb_adr_i    ( wb_rdm_adr_o ),
        .i4_wb_adr_i    ( wb_rdm_adr_o ),
        .i4_wb_sel_i    ( wb_rdm_sel_o ),
        .i4_wb_sel_i    ( wb_rdm_sel_o ),
        .i4_wb_we_i     ( wb_rdm_we_o  ),
        .i4_wb_we_i     ( wb_rdm_we_o  ),
        .i4_wb_dat_i    ( wb_rdm_dat_o ),
        .i4_wb_dat_i    ( wb_rdm_dat_o ),
        .i4_wb_dat_o    ( wb_rdm_dat_i ),
        .i4_wb_dat_o    ( wb_rdm_dat_i ),
Line 938... Line 845...
        .i4_wb_err_o    ( wb_rdm_err_i ),
        .i4_wb_err_o    ( wb_rdm_err_i ),
 
 
        // WISHBONE Initiator 5
        // WISHBONE Initiator 5
        .i5_wb_cyc_i    ( wb_rim_cyc_o ),
        .i5_wb_cyc_i    ( wb_rim_cyc_o ),
        .i5_wb_stb_i    ( wb_rim_stb_o ),
        .i5_wb_stb_i    ( wb_rim_stb_o ),
        .i5_wb_cab_i    ( wb_rim_cab_o ),
 
        .i5_wb_adr_i    ( wb_rim_adr_o ),
        .i5_wb_adr_i    ( wb_rim_adr_o ),
        .i5_wb_sel_i    ( wb_rim_sel_o ),
        .i5_wb_sel_i    ( wb_rim_sel_o ),
        .i5_wb_we_i     ( wb_rim_we_o  ),
        .i5_wb_we_i     ( wb_rim_we_o  ),
        .i5_wb_dat_i    ( wb_rim_dat_o ),
        .i5_wb_dat_i    ( wb_rim_dat_o ),
        .i5_wb_dat_o    ( wb_rim_dat_i ),
        .i5_wb_dat_o    ( wb_rim_dat_i ),
Line 950... Line 856...
        .i5_wb_err_o    ( wb_rim_err_i ),
        .i5_wb_err_o    ( wb_rim_err_i ),
 
 
        // WISHBONE Initiator 6
        // WISHBONE Initiator 6
        .i6_wb_cyc_i    ( 1'b0 ),
        .i6_wb_cyc_i    ( 1'b0 ),
        .i6_wb_stb_i    ( 1'b0 ),
        .i6_wb_stb_i    ( 1'b0 ),
        .i6_wb_cab_i    ( 1'b0 ),
 
        .i6_wb_adr_i    ( 32'h0000_0000 ),
        .i6_wb_adr_i    ( 32'h0000_0000 ),
        .i6_wb_sel_i    ( 4'b0000 ),
        .i6_wb_sel_i    ( 4'b0000 ),
        .i6_wb_we_i     ( 1'b0 ),
        .i6_wb_we_i     ( 1'b0 ),
        .i6_wb_dat_i    ( 32'h0000_0000 ),
        .i6_wb_dat_i    ( 32'h0000_0000 ),
        .i6_wb_dat_o    ( ),
        .i6_wb_dat_o    ( ),
Line 962... Line 867...
        .i6_wb_err_o    ( ),
        .i6_wb_err_o    ( ),
 
 
        // WISHBONE Initiator 7
        // WISHBONE Initiator 7
        .i7_wb_cyc_i    ( 1'b0 ),
        .i7_wb_cyc_i    ( 1'b0 ),
        .i7_wb_stb_i    ( 1'b0 ),
        .i7_wb_stb_i    ( 1'b0 ),
        .i7_wb_cab_i    ( 1'b0 ),
 
        .i7_wb_adr_i    ( 32'h0000_0000 ),
        .i7_wb_adr_i    ( 32'h0000_0000 ),
        .i7_wb_sel_i    ( 4'b0000 ),
        .i7_wb_sel_i    ( 4'b0000 ),
        .i7_wb_we_i     ( 1'b0 ),
        .i7_wb_we_i     ( 1'b0 ),
        .i7_wb_dat_i    ( 32'h0000_0000 ),
        .i7_wb_dat_i    ( 32'h0000_0000 ),
        .i7_wb_dat_o    ( ),
        .i7_wb_dat_o    ( ),
Line 974... Line 878...
        .i7_wb_err_o    ( ),
        .i7_wb_err_o    ( ),
 
 
        // WISHBONE Target 0
        // WISHBONE Target 0
        .t0_wb_cyc_o    ( wb_ss_cyc_i ),
        .t0_wb_cyc_o    ( wb_ss_cyc_i ),
        .t0_wb_stb_o    ( wb_ss_stb_i ),
        .t0_wb_stb_o    ( wb_ss_stb_i ),
        .t0_wb_cab_o    ( wb_ss_cab_i ),
 
        .t0_wb_adr_o    ( wb_ss_adr_i ),
        .t0_wb_adr_o    ( wb_ss_adr_i ),
        .t0_wb_sel_o    ( wb_ss_sel_i ),
        .t0_wb_sel_o    ( wb_ss_sel_i ),
        .t0_wb_we_o     ( wb_ss_we_i  ),
        .t0_wb_we_o     ( wb_ss_we_i  ),
        .t0_wb_dat_o    ( wb_ss_dat_i ),
        .t0_wb_dat_o    ( wb_ss_dat_i ),
        .t0_wb_dat_i    ( wb_ss_dat_o ),
        .t0_wb_dat_i    ( wb_ss_dat_o ),
Line 986... Line 889...
        .t0_wb_err_i    ( wb_ss_err_o ),
        .t0_wb_err_i    ( wb_ss_err_o ),
 
 
        // WISHBONE Target 1
        // WISHBONE Target 1
        .t1_wb_cyc_o    ( wb_fs_cyc_i ),
        .t1_wb_cyc_o    ( wb_fs_cyc_i ),
        .t1_wb_stb_o    ( wb_fs_stb_i ),
        .t1_wb_stb_o    ( wb_fs_stb_i ),
        .t1_wb_cab_o    ( wb_fs_cab_i ),
 
        .t1_wb_adr_o    ( wb_fs_adr_i ),
        .t1_wb_adr_o    ( wb_fs_adr_i ),
        .t1_wb_sel_o    ( wb_fs_sel_i ),
        .t1_wb_sel_o    ( wb_fs_sel_i ),
        .t1_wb_we_o     ( wb_fs_we_i  ),
        .t1_wb_we_o     ( wb_fs_we_i  ),
        .t1_wb_dat_o    ( wb_fs_dat_i ),
        .t1_wb_dat_o    ( wb_fs_dat_i ),
        .t1_wb_dat_i    ( wb_fs_dat_o ),
        .t1_wb_dat_i    ( wb_fs_dat_o ),
Line 998... Line 900...
        .t1_wb_err_i    ( wb_fs_err_o ),
        .t1_wb_err_i    ( wb_fs_err_o ),
 
 
        // WISHBONE Target 2
        // WISHBONE Target 2
        .t2_wb_cyc_o    ( wb_sp_cyc_i ),
        .t2_wb_cyc_o    ( wb_sp_cyc_i ),
        .t2_wb_stb_o    ( wb_sp_stb_i ),
        .t2_wb_stb_o    ( wb_sp_stb_i ),
        .t2_wb_cab_o    ( wb_sp_cab_i ),
 
        .t2_wb_adr_o    ( wb_sp_adr_i ),
        .t2_wb_adr_o    ( wb_sp_adr_i ),
        .t2_wb_sel_o    ( wb_sp_sel_i ),
        .t2_wb_sel_o    ( wb_sp_sel_i ),
        .t2_wb_we_o     ( wb_sp_we_i  ),
        .t2_wb_we_o     ( wb_sp_we_i  ),
        .t2_wb_dat_o    ( wb_sp_dat_i ),
        .t2_wb_dat_o    ( wb_sp_dat_i ),
        .t2_wb_dat_i    ( wb_sp_dat_o ),
        .t2_wb_dat_i    ( wb_sp_dat_o ),
Line 1010... Line 911...
        .t2_wb_err_i    ( wb_sp_err_o ),
        .t2_wb_err_i    ( wb_sp_err_o ),
 
 
        // WISHBONE Target 3
        // WISHBONE Target 3
        .t3_wb_cyc_o    ( wb_es_cyc_i ),
        .t3_wb_cyc_o    ( wb_es_cyc_i ),
        .t3_wb_stb_o    ( wb_es_stb_i ),
        .t3_wb_stb_o    ( wb_es_stb_i ),
        .t3_wb_cab_o    ( wb_es_cab_i ),
 
        .t3_wb_adr_o    ( wb_es_adr_i ),
        .t3_wb_adr_o    ( wb_es_adr_i ),
        .t3_wb_sel_o    ( wb_es_sel_i ),
        .t3_wb_sel_o    ( wb_es_sel_i ),
        .t3_wb_we_o     ( wb_es_we_i  ),
        .t3_wb_we_o     ( wb_es_we_i  ),
        .t3_wb_dat_o    ( wb_es_dat_i ),
        .t3_wb_dat_o    ( wb_es_dat_i ),
        .t3_wb_dat_i    ( wb_es_dat_o ),
        .t3_wb_dat_i    ( wb_es_dat_o ),
Line 1022... Line 922...
        .t3_wb_err_i    ( wb_es_err_o ),
        .t3_wb_err_i    ( wb_es_err_o ),
 
 
        // WISHBONE Target 4
        // WISHBONE Target 4
        .t4_wb_cyc_o    ( ),
        .t4_wb_cyc_o    ( ),
        .t4_wb_stb_o    ( ),
        .t4_wb_stb_o    ( ),
        .t4_wb_cab_o    ( ),
 
        .t4_wb_adr_o    ( ),
        .t4_wb_adr_o    ( ),
        .t4_wb_sel_o    ( ),
        .t4_wb_sel_o    ( ),
        .t4_wb_we_o     ( ),
        .t4_wb_we_o     ( ),
        .t4_wb_dat_o    ( ),
        .t4_wb_dat_o    ( ),
        .t4_wb_dat_i    ( 32'h0000_0000 ),
        .t4_wb_dat_i    ( 32'h0000_0000 ),
Line 1034... Line 933...
        .t4_wb_err_i    ( 1'b1 ),
        .t4_wb_err_i    ( 1'b1 ),
 
 
        // WISHBONE Target 5
        // WISHBONE Target 5
        .t5_wb_cyc_o    ( wb_us_cyc_i ),
        .t5_wb_cyc_o    ( wb_us_cyc_i ),
        .t5_wb_stb_o    ( wb_us_stb_i ),
        .t5_wb_stb_o    ( wb_us_stb_i ),
        .t5_wb_cab_o    ( wb_us_cab_i ),
 
        .t5_wb_adr_o    ( wb_us_adr_i ),
        .t5_wb_adr_o    ( wb_us_adr_i ),
        .t5_wb_sel_o    ( wb_us_sel_i ),
        .t5_wb_sel_o    ( wb_us_sel_i ),
        .t5_wb_we_o     ( wb_us_we_i  ),
        .t5_wb_we_o     ( wb_us_we_i  ),
        .t5_wb_dat_o    ( wb_us_dat_i ),
        .t5_wb_dat_o    ( wb_us_dat_i ),
        .t5_wb_dat_i    ( wb_us_dat_o ),
        .t5_wb_dat_i    ( wb_us_dat_o ),
Line 1046... Line 944...
        .t5_wb_err_i    ( wb_us_err_o ),
        .t5_wb_err_i    ( wb_us_err_o ),
 
 
        // WISHBONE Target 6
        // WISHBONE Target 6
        .t6_wb_cyc_o    ( ),
        .t6_wb_cyc_o    ( ),
        .t6_wb_stb_o    ( ),
        .t6_wb_stb_o    ( ),
        .t6_wb_cab_o    ( ),
 
        .t6_wb_adr_o    ( ),
        .t6_wb_adr_o    ( ),
        .t6_wb_sel_o    ( ),
        .t6_wb_sel_o    ( ),
        .t6_wb_we_o     ( ),
        .t6_wb_we_o     ( ),
        .t6_wb_dat_o    ( ),
        .t6_wb_dat_o    ( ),
        .t6_wb_dat_i    ( 32'h0000_0000 ),
        .t6_wb_dat_i    ( 32'h0000_0000 ),
Line 1058... Line 955...
        .t6_wb_err_i    ( 1'b1 ),
        .t6_wb_err_i    ( 1'b1 ),
 
 
        // WISHBONE Target 7
        // WISHBONE Target 7
        .t7_wb_cyc_o    ( ),
        .t7_wb_cyc_o    ( ),
        .t7_wb_stb_o    ( ),
        .t7_wb_stb_o    ( ),
        .t7_wb_cab_o    ( ),
 
        .t7_wb_adr_o    ( ),
        .t7_wb_adr_o    ( ),
        .t7_wb_sel_o    ( ),
        .t7_wb_sel_o    ( ),
        .t7_wb_we_o     ( ),
        .t7_wb_we_o     ( ),
        .t7_wb_dat_o    ( ),
        .t7_wb_dat_o    ( ),
        .t7_wb_dat_i    ( 32'h0000_0000 ),
        .t7_wb_dat_i    ( 32'h0000_0000 ),
Line 1070... Line 966...
        .t7_wb_err_i    ( 1'b1 ),
        .t7_wb_err_i    ( 1'b1 ),
 
 
        // WISHBONE Target 8
        // WISHBONE Target 8
        .t8_wb_cyc_o    ( ),
        .t8_wb_cyc_o    ( ),
        .t8_wb_stb_o    ( ),
        .t8_wb_stb_o    ( ),
        .t8_wb_cab_o    ( ),
 
        .t8_wb_adr_o    ( ),
        .t8_wb_adr_o    ( ),
        .t8_wb_sel_o    ( ),
        .t8_wb_sel_o    ( ),
        .t8_wb_we_o     ( ),
        .t8_wb_we_o     ( ),
        .t8_wb_dat_o    ( ),
        .t8_wb_dat_o    ( ),
        .t8_wb_dat_i    ( 32'h0000_0000 ),
        .t8_wb_dat_i    ( 32'h0000_0000 ),

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