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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [xilinx_dcm.v] - Diff between revs 62 and 88

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Rev 62 Rev 88
Line 51... Line 51...
wire CLKIN_IBUFG;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLK0_BUF;
wire CLKFB_IN;
wire CLKFB_IN;
wire CLKDV_BUF;
wire CLKDV_BUF;
 
 
 
`ifdef XILINX_FPGA
 
 
IBUFG CLKIN_IBUFG_INST (
IBUFG CLKIN_IBUFG_INST (
        .I(CLKIN_IN),
        .I(CLKIN_IN),
        .O(CLKIN_IBUFG)
        .O(CLKIN_IBUFG)
);
);
 
 
Line 216... Line 218...
        .PSINCDEC(1'b0),                        // Dynamic phase adjust increment/decrement
        .PSINCDEC(1'b0),                        // Dynamic phase adjust increment/decrement
        .RST(1'b0)                              // DCM asynchronous reset input
        .RST(1'b0)                              // DCM asynchronous reset input
);
);
 
 
`endif  // !XILINX_DLL/XILINX_DCM/XILINX_DCM_SP/XILINX_DCM_ADV
`endif  // !XILINX_DLL/XILINX_DCM/XILINX_DCM_SP/XILINX_DCM_ADV
 
`endif  // !XILINX_FPGA
 
 
 
 
endmodule
endmodule
 
 
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