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[/] [minsoc/] [trunk/] [syn/] [xilinx/] [Makefile] - Diff between revs 73 and 85

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Rev 73 Rev 85
?rev1line?
?rev2line?
 
MINSOC = ../
 
MINSOC_DEFINES = ${MINSOC}/backend
 
MINSOC_RTL = ${MINSOC}/rtl/verilog
 
MINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startup
 
UART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilog
 
ADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/Hardware
 
DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog
 
OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog
 
ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog
 
BUILD_SUPPORT = $(MINSOC)/syn/buildSupport
 
 
 
help:
 
        @echo "  all: Synthesize and implement the SoC, then generate a bit stream"
 
        @echo ""
 
        @echo "  soc: Synthesize the SoC"
 
        @echo "  translate: Convert the SoC's ngc file to an ngd file for mapping"
 
        @echo "  map: Express the SoC netlist in the target hardware"
 
        @echo "  par: Place the target hardware, then route the wires"
 
        @echo "  bitgen: Generate a programming file for the target FPGA"
 
        @echo ""
 
        @echo "  modules: Synthesize OR1200 processor, debug interface, UART and Ethernet controllers"
 
        @echo "  or1200: Synthesize the OR1200 processor"
 
        @echo "  debug: Synthesize the debug interface"
 
        @echo "  uart: Synthesize the UART"
 
        @echo "  eth: Synthesize the Ethernet controller"
 
        @echo ""
 
        @echo "  clean: Delete all superfluous files generated by Xilinx tools"
 
        @echo "  distclean: Delete all generated files"
 
 
 
all: minsoc.bit
 
soc: minsoc_top.ngc
 
translate: minsoc.ngd
 
map: minsoc.ncd
 
par: minsoc_par.ncd
 
bitgen: minsoc.bit
 
modules: or1200 debug uart eth
 
MODULES = or1200_top.ngc adbg_top.ngc uart_top.ngc ethmac.ngc
 
 
 
prepare:
 
        rm -rf xst
 
        mkdir xst
 
clean:
 
        rm -rf _xmsgs xst xlnx_auto_0_xdb
 
        rm -rf *.xst *.xrpt *.srp *.lso *.log *.bld *.lst *.twr *.ise *.map *.mrp *.ngm *.pcf *.psr *.xml *.pad *.par *.ptwx *.bgn *.unroutes *.xpi minsoc_par_pad* *.xwbt *.html
 
distclean:
 
        rm -rf *.ngc *.ncd *.ngd *.bit
 
        make clean
 
 
 
minsoc_top.ngc: ${MINSOC_RTL}/*.v ${MINSOC_DEFINES}/minsoc_defines.v $(BUILD_SUPPORT)/minsoc_top.xst $(BUILD_SUPPORT)/minsoc_top.prj
 
        make prepare
 
        xst -ifn "$(BUILD_SUPPORT)/minsoc_top.xst"
 
 
 
uart: uart_top.ngc
 
uart_top.ngc: ${UART_RTL}/*.v $(BUILD_SUPPORT)/uart_top.xst $(BUILD_SUPPORT)/uart_top.prj
 
        make prepare
 
        xst -ifn "$(BUILD_SUPPORT)/uart_top.xst"
 
 
 
eth: ethmac.ngc
 
ethmac.ngc: ${ETH_RTL}/*.v $(BUILD_SUPPORT)/ethmac.xst $(BUILD_SUPPORT)/ethmac.prj
 
        make prepare
 
        xst -ifn "$(BUILD_SUPPORT)/ethmac.xst"
 
 
 
debug: adbg_top.ngc
 
adbg_top.ngc: ${DEBUG_RTL}/*.v $(BUILD_SUPPORT)/adbg_top.xst $(BUILD_SUPPORT)/adbg_top.prj
 
        make prepare
 
        xst -ifn "$(BUILD_SUPPORT)/adbg_top.xst"
 
 
 
or1200: or1200_top.ngc
 
or1200_top.ngc: ${OR1200_RTL}/*.v $(BUILD_SUPPORT)/or1200_top.xst $(BUILD_SUPPORT)/or1200_top.prj
 
        make prepare
 
        xst -ifn "$(BUILD_SUPPORT)/or1200_top.xst"
 
 
 
minsoc.ngd: ${MINSOC}/backend/CONSTRAINT_FILE minsoc_top.ngc $(MODULES)
 
        ngdbuild -p DEVICE_PART -uc ${MINSOC}/backend/CONSTRAINT_FILE -aul minsoc_top.ngc minsoc.ngd
 
 
 
minsoc.ncd: minsoc.ngd
 
        map -bp -timing -cm speed -equivalent_register_removal on -logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd
 
 
 
minsoc_par.ncd: minsoc.ncd
 
        par -ol high -w -xe n minsoc.ncd minsoc_par.ncd
 
 
 
minsoc.bit: minsoc_par.ncd
 
        bitgen -d -w minsoc_par.ncd minsoc.bit

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