| Line 26... |
Line 26... |
input [31:0] A, B,
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input [31:0] A, B,
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input [4:0] Operation,
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input [4:0] Operation,
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input signed [4:0] Shamt,
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input signed [4:0] Shamt,
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output reg signed [31:0] Result,
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output reg signed [31:0] Result,
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output BZero, // Used for Movc
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output BZero, // Used for Movc
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output reg EXC_Ov
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output reg EXC_Ov,
|
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output ALU_Stall // Stalls due to long ALU operations
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);
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);
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|
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`include "MIPS_Parameters.v"
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`include "MIPS_Parameters.v"
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|
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/***
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/***
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| Line 41... |
Line 42... |
chosen to implement various functions, but there is certainly room to improve
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chosen to implement various functions, but there is certainly room to improve
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the speed of arithmetic operations. The ALU could also be placed in a separate
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the speed of arithmetic operations. The ALU could also be placed in a separate
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pipeline stage after the Execute forwarding has completed.
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pipeline stage after the Execute forwarding has completed.
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***/
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***/
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wire signed [31:0] As = A;
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wire signed [31:0] Bs = B;
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reg [63:0] HILO;
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/***
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wire [31:0] HI = HILO[63:32];
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Divider Logic:
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wire [31:0] LO = HILO[31:0];
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wire HILO_Commit = ~(EX_Stall | EX_Flush);
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wire AddSub_Add = ((Operation == AluOp_Add) | (Operation == AluOp_Addu));
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wire signed [31:0] AddSub_Result = (AddSub_Add) ? (A + B) : (A - B);
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wire signed [63:0] Mult_Result = As * Bs;
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The hardware divider requires 32 cycles to complete. Because it writes its
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wire [63:0] Multu_Result = A * B;
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results to HILO and not to the pipeline, the pipeline can proceed without
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stalling. When a later instruction tries to access HILO, the pipeline will
|
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stall if the divide operation has not yet completed.
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***/
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reg [5:0] CLO_Result, CLZ_Result;
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// Internal state registers
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reg [63:0] HILO;
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reg HILO_Access; // Behavioral; not DFFs
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reg [5:0] CLO_Result, CLZ_Result; // Behavioral; not DFFs
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reg div_fsm;
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// Internal signals
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wire [31:0] HI, LO;
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wire HILO_Commit;
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wire signed [31:0] As, Bs;
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wire AddSub_Add;
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wire signed [31:0] AddSub_Result;
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wire signed [63:0] Mult_Result;
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wire [63:0] Multu_Result;
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wire [31:0] Quotient;
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wire [31:0] Remainder;
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wire Div_Stall;
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wire Div_Start, Divu_Start;
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wire DivOp;
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wire Div_Commit;
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// Assignments
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assign HI = HILO[63:32];
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assign LO = HILO[31:0];
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assign HILO_Commit = ~(EX_Stall | EX_Flush);
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assign As = A;
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assign Bs = B;
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assign AddSub_Add = ((Operation == AluOp_Add) | (Operation == AluOp_Addu));
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assign AddSub_Result = (AddSub_Add) ? (A + B) : (A - B);
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assign Mult_Result = As * Bs;
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assign Multu_Result = A * B;
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assign BZero = (B == 32'h00000000);
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assign BZero = (B == 32'h00000000);
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assign DivOp = (Operation == AluOp_Div) || (Operation == AluOp_Divu);
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assign Div_Commit = (div_fsm == 1'b1) && (Div_Stall == 1'b0);
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assign Div_Start = (div_fsm == 1'b0) && (Operation == AluOp_Div) && (HILO_Commit == 1'b1);
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assign Divu_Start = (div_fsm == 1'b0) && (Operation == AluOp_Divu) && (HILO_Commit == 1'b1);
|
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assign ALU_Stall = (div_fsm == 1'b1) && (HILO_Access == 1'b1);
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|
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always @(*) begin
|
always @(*) begin
|
case (Operation)
|
case (Operation)
|
AluOp_Add : Result <= AddSub_Result;
|
AluOp_Add : Result <= AddSub_Result;
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AluOp_Addu : Result <= AddSub_Result;
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AluOp_Addu : Result <= AddSub_Result;
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AluOp_And : Result <= A & B;
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AluOp_And : Result <= A & B;
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AluOp_Clo : Result <= {26'b0, CLO_Result};
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AluOp_Clo : Result <= {26'b0, CLO_Result};
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AluOp_Clz : Result <= {26'b0, CLZ_Result};
|
AluOp_Clz : Result <= {26'b0, CLZ_Result};
|
AluOp_Div : Result <= 32'hdeafbeef; // XXX implement division
|
|
AluOp_Divu : Result <= 32'hdeadbeef; // XXX implement division
|
|
AluOp_Mfhi : Result <= HI;
|
AluOp_Mfhi : Result <= HI;
|
AluOp_Mflo : Result <= LO;
|
AluOp_Mflo : Result <= LO;
|
AluOp_Mul : Result <= Mult_Result[31:0];
|
AluOp_Mul : Result <= Mult_Result[31:0];
|
AluOp_Nor : Result <= ~(A | B);
|
AluOp_Nor : Result <= ~(A | B);
|
AluOp_Or : Result <= A | B;
|
AluOp_Or : Result <= A | B;
|
| Line 94... |
Line 124... |
|
|
always @(posedge clock) begin
|
always @(posedge clock) begin
|
if (reset) begin
|
if (reset) begin
|
HILO <= 64'h00000000_00000000;
|
HILO <= 64'h00000000_00000000;
|
end
|
end
|
|
else if (Div_Commit) begin
|
|
HILO <= {Remainder, Quotient};
|
|
end
|
else if (HILO_Commit) begin
|
else if (HILO_Commit) begin
|
case (Operation)
|
case (Operation)
|
AluOp_Mult : HILO <= Mult_Result;
|
AluOp_Mult : HILO <= Mult_Result;
|
AluOp_Multu : HILO <= Multu_Result;
|
AluOp_Multu : HILO <= Multu_Result;
|
AluOp_Madd : HILO <= HILO + Mult_Result;
|
AluOp_Madd : HILO <= HILO + Mult_Result;
|
| Line 112... |
Line 145... |
else begin
|
else begin
|
HILO <= HILO;
|
HILO <= HILO;
|
end
|
end
|
end
|
end
|
|
|
|
// Detect accesses to HILO. RAW and WAW hazards are possible while a
|
|
// divide operation is computing, so reads and writes to HILO must stall
|
|
// while the divider is busy.
|
|
// (This logic could be put into an earlier pipeline stage or into the
|
|
// datapath bits to improve timing.)
|
|
always @(Operation) begin
|
|
case (Operation)
|
|
AluOp_Div : HILO_Access <= 1;
|
|
AluOp_Divu : HILO_Access <= 1;
|
|
AluOp_Mfhi : HILO_Access <= 1;
|
|
AluOp_Mflo : HILO_Access <= 1;
|
|
AluOp_Mult : HILO_Access <= 1;
|
|
AluOp_Multu : HILO_Access <= 1;
|
|
AluOp_Madd : HILO_Access <= 1;
|
|
AluOp_Maddu : HILO_Access <= 1;
|
|
AluOp_Msub : HILO_Access <= 1;
|
|
AluOp_Msubu : HILO_Access <= 1;
|
|
AluOp_Mthi : HILO_Access <= 1;
|
|
AluOp_Mtlo : HILO_Access <= 1;
|
|
default : HILO_Access <= 0;
|
|
endcase
|
|
end
|
|
|
|
// Divider FSM: The divide unit is either available or busy.
|
|
always @(posedge clock) begin
|
|
if (reset) begin
|
|
div_fsm <= 2'd0;
|
|
end
|
|
else begin
|
|
case (div_fsm)
|
|
1'd0 : div_fsm <= (DivOp & HILO_Commit) ? 1'd1 : 1'd0;
|
|
1'd1 : div_fsm <= (~Div_Stall) ? 1'd0 : 1'd1;
|
|
endcase
|
|
end
|
|
end
|
|
|
// Detect overflow for signed operations. Note that MIPS32 has no overflow
|
// Detect overflow for signed operations. Note that MIPS32 has no overflow
|
// detection for multiplication/division operations.
|
// detection for multiplication/division operations.
|
always @(*) begin
|
always @(*) begin
|
case (Operation)
|
case (Operation)
|
AluOp_Add : EXC_Ov <= ((A[31] ~^ B[31]) & (A[31] ^ AddSub_Result[31]));
|
AluOp_Add : EXC_Ov <= ((A[31] ~^ B[31]) & (A[31] ^ AddSub_Result[31]));
|
AluOp_Sub : EXC_Ov <= ((A[31] ^ B[31]) & (A[31] ^ AddSub_Result[31]));
|
AluOp_Sub : EXC_Ov <= ((A[31] ^ B[31]) & (A[31] ^ AddSub_Result[31]));
|
default : EXC_Ov <= 0;
|
default : EXC_Ov <= 0;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
// Count Leading Ones
|
// Count Leading Ones
|
always @(A) begin
|
always @(A) begin
|
casex (A)
|
casex (A)
|
32'b0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd0;
|
32'b0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd0;
|
32'b10xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd1;
|
32'b10xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd1;
|
| Line 202... |
Line 270... |
32'b0000_0000_0000_0000_0000_0000_0000_0001 : CLZ_Result <= 6'd31;
|
32'b0000_0000_0000_0000_0000_0000_0000_0001 : CLZ_Result <= 6'd31;
|
32'b0000_0000_0000_0000_0000_0000_0000_0000 : CLZ_Result <= 6'd32;
|
32'b0000_0000_0000_0000_0000_0000_0000_0000 : CLZ_Result <= 6'd32;
|
default : CLZ_Result <= 6'd0;
|
default : CLZ_Result <= 6'd0;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
// Multicycle divide unit
|
|
Divide Divider (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.OP_div (Div_Start),
|
|
.OP_divu (Divu_Start),
|
|
.Dividend (A),
|
|
.Divisor (B),
|
|
.Quotient (Quotient),
|
|
.Remainder (Remainder),
|
|
.Stall (Div_Stall)
|
|
);
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
