MIPS32-R1 SoC HOWTO
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MIPS32-R1 SoC HOWTO
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This document is a step-by-step procedure for building the MIPS32 hardware
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This document is a step-by-step procedure for building the MIPS32 hardware
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and software and running it on the XUPV5-LX110T FPGA development board. With
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and software and running it on the XUPV5-LX110T FPGA development board. With
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minimal changes, other hardware platforms may be used as well (see FAQ).
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minimal changes, other hardware platforms may be used as well (see FAQ).
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Procedure
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Procedure
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1. Build the software toolchain. Instructions for doing this are located
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1. Build the software toolchain. Instructions for doing this are located
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in the "Software/toolchain" directory.
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in the "Software/toolchain" directory.
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2. Open the project file "MIPS32-Pipelined-Hw.xise" located in the
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2. Open the project file "MIPS32-Pipelined-Hw.xise" located in the
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"Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw" directory. This is
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"Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw" directory. This is
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a Xilinx ISE 14.1 project file.
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a Xilinx ISE 14.1 project file.
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3. Build the hardware project and generate the programming .bit file.
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3. Build the Block RAM core by using the Block Memory Generator in
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the Core Generator. See details below.
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4. Build the hardware project and generate the programming .bit file.
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Send the programming file to the board through Impact (you may need
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Send the programming file to the board through Impact (you may need
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to create a new Impact project file for your system, but no options
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to create a new Impact project file for your system, but no options
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are needed other than the configuration .bit file targeted for the
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are needed other than the configuration .bit file targeted for the
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Virtex-5 device). A default program built into the BRAM will print
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Virtex-5 device). A default program built into the BRAM will print
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a hello message to the LCD screen.
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a hello message to the LCD screen.
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Alternatively, a pre-built .bit file is located in the
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Alternatively, a pre-built .bit file is located in the
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"Hardware/XUPV5-LX110T_SoC" directory.
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"Hardware/XUPV5-LX110T_SoC" directory. It is timed conservatively
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at 33 MHz (66 MHz bus).
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4. Compile any of the software demos located in "Software/demos" using
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5. Compile any of the software demos located in "Software/demos" using
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the Makefile included with the demo. One of the output files from
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the Makefile included with the demo. One of the output files from
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the compilation will have a .xum extension. This is a binary file that
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the compilation will have a .xum extension. This is a binary file that
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contains the code and data for the program. Use the XUM Bootloader
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contains the code and data for the program. Use the XUM Bootloader
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software (Windows) to send the .xum file over a serial port to the
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software (Windows) to send the .xum file over a serial port to the
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FPGA. When the program is sent, the CPU will reset and run it.
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FPGA. When the program is sent, the CPU will reset and run it.
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Rebuilding the Block RAM
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Rebuilding the Block RAM
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If you need to recreate the Block RAM core for any reason, the following
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The following settings will allow you to build the Block RAM module
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settings will allow you to do it (assuming Xilinx Block Memory Generator
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and add a default program to it assuming Xilinx Block Memory Generator
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version 7.1): True Dual Port RAM, Common Clock, Byte Write Enable of 8
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version 7.1): True Dual Port RAM, Common Clock, Byte Write Enable of 8
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bits, Write/Read width of 32 bits, Write depth of 151552 (for full
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bits, Write/Read width of 32 bits, Write depth of 151552 (for full
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592 KB), Always Enabled, same options for port B, Register Port A Output
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592 KB), Always Enabled, same options for port B, Register Port A Output
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of Memory Primitives AND Memory Core (for 2R version, this can be
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of Memory Primitives AND Memory Core (for 2R version, this can be
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customized), same settings for Port B, fill remaining locations with
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customized), same settings for Port B, fill remaining locations with
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0x00000000, optionally load a .coe file with initial memory contents,
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0x00000000, optionally load a .coe file with initial memory contents,
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use RSTA and RSTB. The file 'Boot.coe' provides the simple hello message
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use RSTA and RSTB. The file 'Boot.coe' provides the simple hello message
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program.
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program.
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FAQ
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FAQ
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---
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---
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Q: What if I don't have the XUPV5-LX110T board?
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Q: What if I don't have the XUPV5-LX110T board?
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A: If you have the same Virtex 5 FPGA but a different board, all you need
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A: If you have the same Virtex 5 FPGA but a different board, all you need
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to do is update the pin locations in the User Constraints File (.ucf)
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to do is update the pin locations in the User Constraints File (.ucf)
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and either make sure your clock input is 100 MHz or adjust the PLL
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and either make sure your clock input is 100 MHz or adjust the PLL
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in the clocking module of the design accordingly. Note that some
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in the clocking module of the design accordingly. Note that some
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hardware such as the LCD screen or piezo speaker may not be present
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hardware such as the LCD screen or piezo speaker may not be present
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on your board, in which case you should remove them from the design.
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on your board, in which case you should remove them from the design.
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Q: What if I don't have a Virtex 5 FPGA?
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Q: What if I don't have a Virtex 5 FPGA?
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A: Any FPGA can implement this design if it has enough logic resources.
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A: Any FPGA can implement this design if it has enough logic resources.
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There are only two Xilinx-specific modules in the MIPS32 SoC design;
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There are only two Xilinx-specific modules in the MIPS32 SoC design;
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the clocking module and BRAM module. Replace these with whatever suits
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the clocking module and BRAM module. Replace these with whatever suits
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your hardware. Note however that the MIPS32 memory interface uses
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your hardware. Note however that the MIPS32 memory interface uses
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byte-width write enables to memory (4 bits per 32-bit word), so if you
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byte-width write enables to memory (4 bits per 32-bit word), so if you
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use Block Memory or equivalents they must either support this or
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use Block Memory or equivalents they must either support this or
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you must fake it somehow. You must also update the UCF.
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you must fake it somehow. You must also update the UCF.
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Q: What if I don't have or use the Xilinx development tools?
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Q: What if I don't have or use the Xilinx development tools?
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A: If you only care about the MIPS32 processor and not the full SoC, start
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A: If you only care about the MIPS32 processor and not the full SoC, start
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with the "Hardware/MIPS32_Standalone" directory which contains only
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with the "Hardware/MIPS32_Standalone" directory which contains only
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Verilog files. The top-most module is "Processor.v". For the full SoC,
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Verilog files. The top-most module is "Processor.v". For the full SoC,
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copy the "Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src" directory
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copy the "Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src" directory
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to whatever development environment you use. This directory contains
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to whatever development environment you use. This directory contains
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all of the Verilog files with "Top.v" as the head. The "Clocks" and
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all of the Verilog files with "Top.v" as the head. The "Clocks" and
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"BRAM" directories will need to be customized for your environment,
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"BRAM" directories will need to be customized for your environment,
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as well as the pin constraints.
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as well as the pin constraints.
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Q: Is there a non-Windows version of the bootloader?
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Q: Is there a non-Windows version of the bootloader?
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A: No, but the boot protocol is simple and can be implemented for any OS.
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A: No, but the boot protocol is simple and can be implemented for any OS.
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See "Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/
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See "Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/
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uart_bootloader_v2.v" for a description of the protocol. If you
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uart_bootloader_v2.v" for a description of the protocol. If you
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implement another version of the bootloader, please contribute it back
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implement another version of the bootloader, please contribute it back
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to the project.
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to the project.
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