`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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/*
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/*
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* File : Top.v
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* File : Top.v
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* Project : University of Utah, XUM Project MIPS32 core
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* Project : University of Utah, XUM Project MIPS32 core
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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*
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*
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* Modification History:
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* Modification History:
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* Rev Date Initials Description of Change
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* Rev Date Initials Description of Change
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* 1.0 8-Jul-2011 GEA Initial design.
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* 1.0 8-Jul-2011 GEA Initial design.
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*
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*
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* Standards/Formatting:
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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* Verilog 2001, 4 soft tab, wide column.
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*
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*
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* Description:
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* Description:
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* The top-level file for the FPGA. Also known as the 'motherboard,' this
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* The top-level file for the FPGA. Also known as the 'motherboard,' this
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* file connects all processor, memory, clocks, and I/O devices together.
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* file connects all processor, memory, clocks, and I/O devices together.
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* All inputs and outputs correspond to actual FPGA pins.
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* All inputs and outputs correspond to actual FPGA pins.
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*/
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*/
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module Top(
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module Top(
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input clock_100MHz,
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input clock_100MHz,
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input reset_n,
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input reset_n,
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// I/O
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// I/O
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input [7:0] Switch,
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input [7:0] Switch,
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output [14:0] LED,
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output [14:0] LED,
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output [6:0] LCD,
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output [6:0] LCD,
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input UART_Rx,
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input UART_Rx,
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output UART_Tx,
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output UART_Tx,
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inout i2c_scl,
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inout i2c_scl,
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inout i2c_sda,
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inout i2c_sda,
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output Piezo
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output Piezo
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);
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);
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// Clock signals
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// Clock signals
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wire clock, clock2x;
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wire clock, clock2x;
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wire PLL_Locked;
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wire PLL_Locked;
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reg reset;
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reg reset;
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always @(posedge clock) begin
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always @(posedge clock) begin
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reset <= ~reset_n | ~PLL_Locked;
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reset <= ~reset_n | ~PLL_Locked;
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end
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end
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// MIPS Processor Signals
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// MIPS Processor Signals
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reg [31:0] MIPS32_DataMem_In;
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reg [31:0] MIPS32_DataMem_In;
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wire [31:0] MIPS32_DataMem_Out, MIPS32_InstMem_In;
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wire [31:0] MIPS32_DataMem_Out, MIPS32_InstMem_In;
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wire [29:0] MIPS32_DataMem_Address, MIPS32_InstMem_Address;
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wire [29:0] MIPS32_DataMem_Address, MIPS32_InstMem_Address;
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wire [3:0] MIPS32_DataMem_WE;
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wire [3:0] MIPS32_DataMem_WE;
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wire MIPS32_DataMem_Read, MIPS32_InstMem_Read;
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wire MIPS32_DataMem_Read, MIPS32_InstMem_Read;
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reg MIPS32_DataMem_Ready;
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reg MIPS32_DataMem_Ready;
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wire [4:0] MIPS32_Interrupts;
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wire [4:0] MIPS32_Interrupts;
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wire MIPS32_NMI;
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wire MIPS32_NMI;
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wire [7:0] MIPS32_IP;
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wire [7:0] MIPS32_IP;
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wire MIPS32_IO_WE;
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wire MIPS32_IO_WE;
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// BRAM Memory Signals
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// BRAM Memory Signals
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reg [3:0] BRAM_WEA;
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reg [3:0] BRAM_WEA;
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reg BRAM_REA;
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reg BRAM_REA;
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reg [17:0] BRAM_AddrA;
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reg [17:0] BRAM_AddrA;
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reg [31:0] BRAM_DINA;
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reg [31:0] BRAM_DINA;
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wire BRAM_ReadyA;
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wire BRAM_ReadyA;
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wire BRAM_REB;
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wire BRAM_REB;
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wire [3:0] BRAM_WEB;
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wire [3:0] BRAM_WEB;
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wire [31:0] BRAM_DOUTB;
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wire [31:0] BRAM_DOUTB;
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wire BRAM_ReadyB;
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wire BRAM_ReadyB;
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// LCD Signals
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// LCD Signals
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wire [3:0] LCD_WE;
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wire [3:0] LCD_WE;
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wire LCD_Ready;
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wire LCD_Ready;
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// UART Bootloader Signals
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// UART Bootloader Signals
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wire UART_RE;
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wire UART_RE;
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wire UART_WE;
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wire UART_WE;
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wire [16:0] UART_DOUT;
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wire [16:0] UART_DOUT;
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wire UART_Ack;
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wire UART_Ack;
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wire UART_Interrupt;
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wire UART_Interrupt;
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wire UART_BootResetCPU;
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wire UART_BootResetCPU;
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wire [17:0] UART_BootAddress;
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wire [17:0] UART_BootAddress;
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wire [31:0] UART_BootData;
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wire [31:0] UART_BootData;
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wire UART_BootWriteMem_pre;
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wire UART_BootWriteMem_pre;
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wire [3:0] UART_BootWriteMem = (UART_BootWriteMem_pre) ? 4'hF : 4'h0;
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wire [3:0] UART_BootWriteMem = (UART_BootWriteMem_pre) ? 4'hF : 4'h0;
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// I2C Signals
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// I2C Signals
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wire I2C_Ready;
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wire I2C_Ready;
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wire [10:0] I2C_DOUT;
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wire [10:0] I2C_DOUT;
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wire I2C_RE, I2C_WE;
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wire I2C_RE, I2C_WE;
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// Piezo Transducer Signals
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// Piezo Transducer Signals
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wire Piezo_WE;
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wire Piezo_WE;
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wire Piezo_Ready;
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wire Piezo_Ready;
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// LED Signals
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// LED Signals
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wire LED_WE;
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wire LED_WE;
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wire LED_RE;
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wire LED_RE;
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wire [13:0] LED_DOUT;
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wire [13:0] LED_DOUT;
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wire LED_Ready;
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wire LED_Ready;
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wire [13:0] LED_Sw_LEDs;
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wire [13:0] LED_Sw_LEDs;
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// Filtered Switch Input Signals
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// Filtered Switch Input Signals
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wire Switches_RE;
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wire Switches_RE;
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wire Switches_WE;
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wire Switches_WE;
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wire Switches_Ready;
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wire Switches_Ready;
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wire [7:0] Switches_DOUT;
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wire [7:0] Switches_DOUT;
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// Clock Generation
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// Clock Generation
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PLL_100MHz_to_50MHz_100MHz Clock_Generator (
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PLL_100MHz_to_33MHz_66MHz Clock_Generator (
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.CLKIN1_IN (clock_100MHz),
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.CLKIN1_IN (clock_100MHz),
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.RST_IN (1'b0),
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.RST_IN (1'b0),
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.CLKOUT0_OUT (clock),
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.CLKOUT0_OUT (clock),
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.CLKOUT1_OUT (clock2x),
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.CLKOUT1_OUT (clock2x),
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.LOCKED_OUT (PLL_Locked)
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.LOCKED_OUT (PLL_Locked)
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);
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);
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// MIPS-32 Core
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// MIPS-32 Core
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Processor MIPS32 (
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Processor MIPS32 (
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.clock (clock),
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.clock (clock),
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.reset ((reset | UART_BootResetCPU)),
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.reset ((reset | UART_BootResetCPU)),
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.Interrupts (MIPS32_Interrupts),
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.Interrupts (MIPS32_Interrupts),
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.NMI (MIPS32_NMI),
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.NMI (MIPS32_NMI),
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.DataMem_In (MIPS32_DataMem_In),
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.DataMem_In (MIPS32_DataMem_In),
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.DataMem_Ready (MIPS32_DataMem_Ready),
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.DataMem_Ready (MIPS32_DataMem_Ready),
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.DataMem_Read (MIPS32_DataMem_Read),
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.DataMem_Read (MIPS32_DataMem_Read),
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.DataMem_Write (MIPS32_DataMem_WE),
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.DataMem_Write (MIPS32_DataMem_WE),
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.DataMem_Address (MIPS32_DataMem_Address),
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.DataMem_Address (MIPS32_DataMem_Address),
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.DataMem_Out (MIPS32_DataMem_Out),
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.DataMem_Out (MIPS32_DataMem_Out),
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.InstMem_In (MIPS32_InstMem_In),
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.InstMem_In (MIPS32_InstMem_In),
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.InstMem_Address (MIPS32_InstMem_Address),
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.InstMem_Address (MIPS32_InstMem_Address),
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.InstMem_Ready (BRAM_ReadyA),
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.InstMem_Ready (BRAM_ReadyA),
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.InstMem_Read (MIPS32_InstMem_Read),
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.InstMem_Read (MIPS32_InstMem_Read),
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.IP (MIPS32_IP)
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.IP (MIPS32_IP)
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);
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);
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// On-Chip Block RAM
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// On-Chip Block RAM
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BRAM_592KB_Wrapper Memory (
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BRAM_592KB_Wrapper Memory (
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.clock (clock2x),
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.clock (clock2x),
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.reset (reset),
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.reset (reset),
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.rea (BRAM_REA),
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.rea (BRAM_REA),
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.wea (BRAM_WEA),
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.wea (BRAM_WEA),
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.addra (BRAM_AddrA),
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.addra (BRAM_AddrA),
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.dina (BRAM_DINA),
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.dina (BRAM_DINA),
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.douta (MIPS32_InstMem_In),
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.douta (MIPS32_InstMem_In),
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.dreadya (BRAM_ReadyA),
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.dreadya (BRAM_ReadyA),
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.reb (BRAM_REB),
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.reb (BRAM_REB),
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.web (BRAM_WEB),
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.web (BRAM_WEB),
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.addrb (MIPS32_DataMem_Address[17:0]),
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.addrb (MIPS32_DataMem_Address[17:0]),
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.dinb (MIPS32_DataMem_Out),
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.dinb (MIPS32_DataMem_Out),
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.doutb (BRAM_DOUTB),
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.doutb (BRAM_DOUTB),
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.dreadyb (BRAM_ReadyB)
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.dreadyb (BRAM_ReadyB)
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);
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);
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// 16x2 LCD Display Screen
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// 16x2 LCD Display Screen
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LCD LCD_Screen (
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LCD LCD_Screen (
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.clock_100MHz (clock2x),
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.clock_100MHz (clock2x),
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.clock_Mem (clock2x),
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.clock_Mem (clock2x),
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.reset (reset),
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.reset (reset),
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.address (MIPS32_DataMem_Address[2:0]),
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.address (MIPS32_DataMem_Address[2:0]),
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.data (MIPS32_DataMem_Out),
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.data (MIPS32_DataMem_Out),
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.writeEnable (LCD_WE),
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.writeEnable (LCD_WE),
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.ack (LCD_Ready),
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.ack (LCD_Ready),
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.LCD (LCD)
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.LCD (LCD)
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);
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);
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// UART + Boot Loader (v2)
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// UART + Boot Loader (v2)
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uart_bootloader UART (
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uart_bootloader UART (
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.clock (clock2x),
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.clock (clock2x),
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.reset (reset),
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.reset (reset),
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.Read (UART_RE),
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.Read (UART_RE),
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.Write (UART_WE),
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.Write (UART_WE),
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.DataIn (MIPS32_DataMem_Out[8:0]),
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.DataIn (MIPS32_DataMem_Out[8:0]),
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.DataOut (UART_DOUT),
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.DataOut (UART_DOUT),
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.Ack (UART_Ack),
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.Ack (UART_Ack),
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.DataReady (UART_Interrupt),
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.DataReady (UART_Interrupt),
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.BootResetCPU (UART_BootResetCPU),
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.BootResetCPU (UART_BootResetCPU),
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.BootWriteMem (UART_BootWriteMem_pre),
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.BootWriteMem (UART_BootWriteMem_pre),
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.BootAddr (UART_BootAddress),
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.BootAddr (UART_BootAddress),
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.BootData (UART_BootData),
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.BootData (UART_BootData),
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.RxD (UART_Rx),
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.RxD (UART_Rx),
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.TxD (UART_Tx)
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.TxD (UART_Tx)
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);
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);
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// I2C Module
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// I2C Module
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I2C_Controller I2C (
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I2C_Controller I2C (
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.clock (clock2x),
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.clock (clock2x),
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.reset (reset),
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.reset (reset),
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.Read (I2C_RE),
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.Read (I2C_RE),
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.Write (I2C_WE),
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.Write (I2C_WE),
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.DataIn (MIPS32_DataMem_Out[12:0]),
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.DataIn (MIPS32_DataMem_Out[12:0]),
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.DataOut (I2C_DOUT),
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.DataOut (I2C_DOUT),
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.Ack (I2C_Ready),
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.Ack (I2C_Ready),
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.i2c_scl (i2c_scl),
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.i2c_scl (i2c_scl),
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.i2c_sda (i2c_sda)
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.i2c_sda (i2c_sda)
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);
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);
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// Piezo-electric Transducer
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// Piezo-electric Transducer
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Piezo_Driver Piezo_Driver (
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Piezo_Driver Piezo_Driver (
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.clock (clock2x),
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.clock (clock2x),
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.reset (reset),
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.reset (reset),
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.data (MIPS32_DataMem_Out[24:0]),
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.data (MIPS32_DataMem_Out[24:0]),
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.Write (Piezo_WE),
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.Write (Piezo_WE),
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.Ack (Piezo_Ready),
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.Ack (Piezo_Ready),
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.Piezo (Piezo)
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.Piezo (Piezo)
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);
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);
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// LEDs
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// LEDs
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LED LEDs (
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LED LEDs (
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.clock (clock2x),
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.clock (clock2x),
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.reset (reset),
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.reset (reset),
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.dataIn (MIPS32_DataMem_Out[14:0]),
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.dataIn (MIPS32_DataMem_Out[14:0]),
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.IP (MIPS32_IP),
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.IP (MIPS32_IP),
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.Write (LED_WE),
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.Write (LED_WE),
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.Read (LED_RE),
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.Read (LED_RE),
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.dataOut (LED_DOUT),
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.dataOut (LED_DOUT),
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.Ack (LED_Ready),
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.Ack (LED_Ready),
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.LED (LED_Sw_LEDs)
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.LED (LED_Sw_LEDs)
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);
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);
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// Filtered Input Switches
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// Filtered Input Switches
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Switches Switches (
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Switches Switches (
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.clock (clock2x),
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.clock (clock2x),
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.reset (reset),
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.reset (reset),
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.Read (Switches_RE),
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.Read (Switches_RE),
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.Write (Switches_WE),
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.Write (Switches_WE),
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.Switch_in (Switch),
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.Switch_in (Switch),
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.Ack (Switches_Ready),
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.Ack (Switches_Ready),
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.Switch_out (Switches_DOUT)
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.Switch_out (Switches_DOUT)
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);
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);
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assign MIPS32_IO_WE = (MIPS32_DataMem_WE == 4'hF) ? 1 : 0;
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assign MIPS32_IO_WE = (MIPS32_DataMem_WE == 4'hF) ? 1 : 0;
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assign MIPS32_Interrupts[4:1] = Switches_DOUT[7:4];
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assign MIPS32_Interrupts[4:1] = Switches_DOUT[7:4];
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assign MIPS32_Interrupts[0] = UART_Interrupt;
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assign MIPS32_Interrupts[0] = UART_Interrupt;
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assign MIPS32_NMI = Switches_DOUT[3];
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assign MIPS32_NMI = Switches_DOUT[3];
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assign LED = {UART_BootResetCPU, LED_Sw_LEDs[13:0]};
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assign LED = {UART_BootResetCPU, LED_Sw_LEDs[13:0]};
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// Allow writes to Instruction Memory Port when bootloading
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// Allow writes to Instruction Memory Port when bootloading
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always @(*) begin
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always @(*) begin
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BRAM_REA <= (UART_BootResetCPU) ? 0 : MIPS32_InstMem_Read;
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BRAM_REA <= (UART_BootResetCPU) ? 0 : MIPS32_InstMem_Read;
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BRAM_WEA <= (UART_BootResetCPU) ? UART_BootWriteMem : 4'h0;
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BRAM_WEA <= (UART_BootResetCPU) ? UART_BootWriteMem : 4'h0;
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BRAM_AddrA <= (UART_BootResetCPU) ? UART_BootAddress : MIPS32_InstMem_Address;
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BRAM_AddrA <= (UART_BootResetCPU) ? UART_BootAddress : MIPS32_InstMem_Address;
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BRAM_DINA <= (UART_BootResetCPU) ? UART_BootData : 32'h0000_0000;
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BRAM_DINA <= (UART_BootResetCPU) ? UART_BootData : 32'h0000_0000;
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end
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end
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always @(*) begin
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always @(*) begin
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case (MIPS32_DataMem_Address[29])
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case (MIPS32_DataMem_Address[29])
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0 : begin
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0 : begin
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MIPS32_DataMem_In <= BRAM_DOUTB;
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MIPS32_DataMem_In <= BRAM_DOUTB;
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MIPS32_DataMem_Ready <= BRAM_ReadyB;
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MIPS32_DataMem_Ready <= BRAM_ReadyB;
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end
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end
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1 : begin
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1 : begin
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// Memory-mapped I/O
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// Memory-mapped I/O
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case (MIPS32_DataMem_Address[28:26])
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case (MIPS32_DataMem_Address[28:26])
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// LCD
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// LCD
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3'b000 : begin
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3'b000 : begin
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MIPS32_DataMem_In <= 32'h0000_0000;
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MIPS32_DataMem_In <= 32'h0000_0000;
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MIPS32_DataMem_Ready <= LCD_Ready;
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MIPS32_DataMem_Ready <= LCD_Ready;
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end
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end
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// I2C
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// I2C
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3'b001 : begin
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3'b001 : begin
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MIPS32_DataMem_In <= {21'h000000, I2C_DOUT[10:0]};
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MIPS32_DataMem_In <= {21'h000000, I2C_DOUT[10:0]};
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MIPS32_DataMem_Ready <= I2C_Ready;
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MIPS32_DataMem_Ready <= I2C_Ready;
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end
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end
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// Piezo
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// Piezo
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3'b010 : begin
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3'b010 : begin
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MIPS32_DataMem_In <= 32'h0000_0000;
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MIPS32_DataMem_In <= 32'h0000_0000;
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MIPS32_DataMem_Ready <= Piezo_Ready;
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MIPS32_DataMem_Ready <= Piezo_Ready;
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end
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end
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// UART
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// UART
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3'b011 : begin
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3'b011 : begin
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MIPS32_DataMem_In <= {15'h0000, UART_DOUT[16:0]};
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MIPS32_DataMem_In <= {15'h0000, UART_DOUT[16:0]};
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MIPS32_DataMem_Ready <= UART_Ack;
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MIPS32_DataMem_Ready <= UART_Ack;
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end
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end
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// LED
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// LED
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3'b100 : begin
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3'b100 : begin
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MIPS32_DataMem_In <= {18'h00000, LED_DOUT[13:0]};
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MIPS32_DataMem_In <= {18'h00000, LED_DOUT[13:0]};
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MIPS32_DataMem_Ready <= LED_Ready;
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MIPS32_DataMem_Ready <= LED_Ready;
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end
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end
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// Switches
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// Switches
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3'b101 : begin
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3'b101 : begin
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MIPS32_DataMem_In <= {24'h000000, Switches_DOUT[7:0]};
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MIPS32_DataMem_In <= {24'h000000, Switches_DOUT[7:0]};
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MIPS32_DataMem_Ready <= Switches_Ready;
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MIPS32_DataMem_Ready <= Switches_Ready;
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end
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end
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default: begin
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default: begin
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MIPS32_DataMem_In <= 32'h0000_0000;
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MIPS32_DataMem_In <= 32'h0000_0000;
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MIPS32_DataMem_Ready <= 0;
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MIPS32_DataMem_Ready <= 0;
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end
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end
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endcase
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endcase
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end
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end
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endcase
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endcase
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end
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end
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|
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// Memory
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// Memory
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assign BRAM_REB = (MIPS32_DataMem_Address[29]) ? 0 : MIPS32_DataMem_Read;
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assign BRAM_REB = (MIPS32_DataMem_Address[29]) ? 0 : MIPS32_DataMem_Read;
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assign BRAM_WEB = (MIPS32_DataMem_Address[29]) ? 4'h0 : MIPS32_DataMem_WE;
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assign BRAM_WEB = (MIPS32_DataMem_Address[29]) ? 4'h0 : MIPS32_DataMem_WE;
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// I/O
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// I/O
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assign LCD_WE = (MIPS32_DataMem_Address[29:26] == 4'b1000) ? MIPS32_DataMem_WE : 4'h0;
|
assign LCD_WE = (MIPS32_DataMem_Address[29:26] == 4'b1000) ? MIPS32_DataMem_WE : 4'h0;
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assign Piezo_WE = (MIPS32_DataMem_Address[29:26] == 4'b1010) ? MIPS32_IO_WE : 0;
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assign Piezo_WE = (MIPS32_DataMem_Address[29:26] == 4'b1010) ? MIPS32_IO_WE : 0;
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assign I2C_WE = (MIPS32_DataMem_Address[29:26] == 4'b1001) ? MIPS32_IO_WE : 0;
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assign I2C_WE = (MIPS32_DataMem_Address[29:26] == 4'b1001) ? MIPS32_IO_WE : 0;
|
assign I2C_RE = (MIPS32_DataMem_Address[29:26] == 4'b1001) ? MIPS32_DataMem_Read : 0;
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assign I2C_RE = (MIPS32_DataMem_Address[29:26] == 4'b1001) ? MIPS32_DataMem_Read : 0;
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assign UART_WE = (MIPS32_DataMem_Address[29:26] == 4'b1011) ? MIPS32_IO_WE : 0;
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assign UART_WE = (MIPS32_DataMem_Address[29:26] == 4'b1011) ? MIPS32_IO_WE : 0;
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assign UART_RE = (MIPS32_DataMem_Address[29:26] == 4'b1011) ? MIPS32_DataMem_Read : 0;
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assign UART_RE = (MIPS32_DataMem_Address[29:26] == 4'b1011) ? MIPS32_DataMem_Read : 0;
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assign LED_WE = (MIPS32_DataMem_Address[29:26] == 4'b1100) ? MIPS32_IO_WE : 0;
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assign LED_WE = (MIPS32_DataMem_Address[29:26] == 4'b1100) ? MIPS32_IO_WE : 0;
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assign LED_RE = (MIPS32_DataMem_Address[29:26] == 4'b1100) ? MIPS32_DataMem_Read : 0;
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assign LED_RE = (MIPS32_DataMem_Address[29:26] == 4'b1100) ? MIPS32_DataMem_Read : 0;
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assign Switches_WE = (MIPS32_DataMem_Address[29:26] == 4'b1101) ? MIPS32_IO_WE : 0;
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assign Switches_WE = (MIPS32_DataMem_Address[29:26] == 4'b1101) ? MIPS32_IO_WE : 0;
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assign Switches_RE = (MIPS32_DataMem_Address[29:26] == 4'b1101) ? MIPS32_DataMem_Read : 0;
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assign Switches_RE = (MIPS32_DataMem_Address[29:26] == 4'b1101) ? MIPS32_DataMem_Read : 0;
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endmodule
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endmodule
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