`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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/*
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/*
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* File : uart_clock.v
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* File : uart_clock.v
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* Project : University of Utah, XUM Project MIPS32 core
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* Project : University of Utah, XUM Project MIPS32 core
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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*
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*
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* Modification History:
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* Modification History:
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* Rev Date Initials Description of Change
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* Rev Date Initials Description of Change
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* 1.0 24-May-2010 GEA Initial design.
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* 1.0 24-May-2010 GEA Initial design.
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*
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*
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* Standards/Formatting:
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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* Verilog 2001, 4 soft tab, wide column.
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*
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*
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* Description:
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* Description:
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* Takes a 100 MHz clock and generates synchronous pulses for 115200 baud
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* Takes a 100 MHz clock and generates synchronous pulses for 115200 baud
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* and 16x 115200 baud (synchronized).
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* and 16x 115200 baud (synchronized).
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*
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*
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* This timing can be adjusted to allow for other baud rates.
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* This timing can be adjusted to allow for other baud rates.
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*/
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*/
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module uart_clock(
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module uart_clock(
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input clock,
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input clock,
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output uart_tick,
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output uart_tick,
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output uart_tick_16x
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output uart_tick_16x
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);
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);
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// 100MHz / (2^13 / 151) == 16 * 115203.857 Hz
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// 100MHz / (2^13 / 151) == 16 * 115203.857 Hz
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// 100MHz / (2^17 / 151) == 115203.857 Hz
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// 100MHz / (2^17 / 151) == 115203.857 Hz
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// 66MHz / (2^14 / 453) == 16 * 115203.857 Hz
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// 66MHz / (2^14 / 453) == 16 * 115203.857 Hz
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// 66MHz / (2^18 / 453) == 115203.857 Hz
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// 66MHz / (2^18 / 453) == 115203.857 Hz
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// 66 MHz version
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reg [14:0] accumulator = 15'h0000;
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always @(posedge clock) begin
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accumulator <= accumulator[13:0] + 453;
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end
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assign uart_tick_16x = accumulator[14];
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/*
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/*
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// 66 MHz version
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// 100 MHz version
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reg [14:0] accumulator = 15'h0000;
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reg [13:0] accumulator = 14'h0000;
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always @(posedge clock) begin
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always @(posedge clock) begin
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accumulator <= accumulator[13:0] + 453;
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accumulator <= accumulator[12:0] + 151;
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end
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end
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assign uart_tick_16x = accumulator[14];
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assign uart_tick_16x = accumulator[13];
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*/
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*/
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// 100 MHz version
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reg [13:0] accumulator = 14'h0000;
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always @(posedge clock) begin
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accumulator <= accumulator[12:0] + 151;
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end
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assign uart_tick_16x = accumulator[13];
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//------------------------------
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//------------------------------
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reg [3:0] uart_16x_count = 4'h0;
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reg [3:0] uart_16x_count = 4'h0;
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always @(posedge clock) begin
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always @(posedge clock) begin
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uart_16x_count <= (uart_tick_16x) ? uart_16x_count + 1 : uart_16x_count;
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uart_16x_count <= (uart_tick_16x) ? uart_16x_count + 1 : uart_16x_count;
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end
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end
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assign uart_tick = (uart_tick_16x==1'b1 && (uart_16x_count == 4'b1111));
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assign uart_tick = (uart_tick_16x==1'b1 && (uart_16x_count == 4'b1111));
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endmodule
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endmodule
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