| Line 80... |
Line 80... |
signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
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signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
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signal ramwaddr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
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signal ramwaddr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
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signal ramenw : STD_LOGIC;
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signal ramenw : STD_LOGIC;
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signal ramraddr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
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signal ramraddr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
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signal pix_inblk_cnt : unsigned(2 downto 0);
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signal pix_inblk_cnt : unsigned(3 downto 0);
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signal pix_inblk_cnt_d1 : unsigned(2 downto 0);
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signal pix_inblk_cnt_d1 : unsigned(3 downto 0);
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signal line_inblk_cnt : unsigned(2 downto 0);
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signal line_inblk_cnt : unsigned(2 downto 0);
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signal read_block_cnt : unsigned(12 downto 0);
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signal read_block_cnt : unsigned(12 downto 0);
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signal read_block_cnt_d1 : unsigned(12 downto 0);
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signal read_block_cnt_d1 : unsigned(12 downto 0);
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signal write_block_cnt : unsigned(12 downto 0);
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signal write_block_cnt : unsigned(12 downto 0);
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| Line 212... |
Line 212... |
else
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else
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fdct_fifo_hf_full <= '0';
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fdct_fifo_hf_full <= '0';
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end if;
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end if;
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fifo_almost_full <= '0';
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fifo_almost_full <= '0';
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if C_EXTRA_LINES = 0 then
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if wr_line_idx = rd_line_idx + C_NUM_LINES-1 then
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if wr_line_idx = rd_line_idx + C_NUM_LINES-1 then
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if pixel_cnt >= unsigned(img_size_x)-1-1 then
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if pixel_cnt >= unsigned(img_size_x)-1-1 then
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fifo_almost_full <= '1';
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fifo_almost_full <= '1';
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end if;
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end if;
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elsif wr_line_idx > rd_line_idx + C_NUM_LINES-1 then
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elsif wr_line_idx > rd_line_idx + C_NUM_LINES-1 then
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fifo_almost_full <= '1';
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fifo_almost_full <= '1';
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end if;
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end if;
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else
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if wr_line_idx > rd_line_idx + C_NUM_LINES-1 then
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fifo_almost_full <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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