OpenCores
URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

[/] [mkjpeg/] [trunk/] [design/] [JFIFGen/] [HeaderRAM.vhd] - Diff between revs 65 and 66

Show entire file | Details | Blame | View Log

Rev 65 Rev 66
Line 1... Line 1...
-- HeaderRam.vhd Khaleghian 8 Nov 2010
LIBRARY ieee, std;
 
USE ieee.std_logic_1164.ALL;
 
USE ieee.numeric_std.ALL;
 
use ieee.std_logic_textio.all;
 
use std.textio.all;
 
 
library ieee;
ENTITY HeaderRam IS
library work;
        GENERIC
use ieee.std_logic_1164.all;
        (
use ieee.std_logic_unsigned.all;
                ADDRESS_WIDTH   : integer := 10;
use work.all;
                DATA_WIDTH              : integer := 8
entity HeaderRam is
 
port (
 
d : in STD_LOGIC_VECTOR(7 downto 0);
 
waddr : in STD_LOGIC_VECTOR(9 downto 0);
 
raddr : in STD_LOGIC_VECTOR(9 downto 0);
 
we : in STD_LOGIC;
 
clk : in STD_LOGIC;
 
q : out STD_LOGIC_VECTOR(7 downto 0)
 
);
);
end HeaderRam;
        PORT
 
        (
 
                clk                             : IN  std_logic;
 
                d                               : IN  std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
 
                waddr                   : IN  std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
 
                raddr                   : IN  std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
 
                we                              : IN  std_logic;
 
                q                               : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0)
 
        );
 
END HeaderRam;
 
 
architecture syn of HeaderRam is
ARCHITECTURE rtl OF HeaderRam IS
type ram_type is array (1023 downto 0) of std_logic_vector (7 downto 0);
 
signal RAM : ram_type;
TYPE RamType IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
signal read_addr: STD_LOGIC_VECTOR(9 downto 0);
 
begin
impure function InitRamFromFile(RamFileName : in string) return RamType is
q <= RAM(conv_integer(read_addr)) ;
        FILE RamFile : text is in RamFileName;
process (clk)
        variable RamFileLine : line;
 
        variable RAM : RamType;
begin
begin
if clk'event and clk = '1'
        for l in RamType'range loop
then
                readline(RamFile, RamFileLine);
if we='1' then
                hread(RamFileLine, RAM(l));
RAM(conv_integer(waddr)) <= d;
        end loop;
end if;
        return RAM;
read_addr <= raddr;
end function;
end if;
 
end process;
--SIGNAL ram_block : RamType := InitRamFromFile("../design/jfifgen/header.hex");
end syn;
SIGNAL ram_block : RamType;
 
attribute ram_init_file : string;
 
attribute ram_init_file of ram_block :
 
signal is "./src/jpg/JFIFGen/header.mif";
 
BEGIN
 
        PROCESS (clk)
 
        BEGIN
 
                IF (clk'event AND clk = '1') THEN
 
                        IF (we = '1') THEN
 
                            ram_block(to_integer(unsigned(waddr))) <= d;
 
                        END IF;
 
 
 
                        q <= ram_block(to_integer(unsigned(raddr)));
 
                END IF;
 
        END PROCESS;
 
END rtl;
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.