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https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk
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| Rev 36 |
Rev 37 |
| Line 101... |
Line 101... |
signal rd_cnt_d2 : unsigned(rd_cnt'range);
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signal rd_cnt_d2 : unsigned(rd_cnt'range);
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signal eoi_cnt : unsigned(1 downto 0);
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signal eoi_cnt : unsigned(1 downto 0);
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signal eoi_wr : std_logic;
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signal eoi_wr : std_logic;
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signal eoi_wr_d1 : std_logic;
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signal eoi_wr_d1 : std_logic;
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component HeaderRam is
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port
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(
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d : in STD_LOGIC_VECTOR(7 downto 0);
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waddr : in STD_LOGIC_VECTOR(9 downto 0);
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raddr : in STD_LOGIC_VECTOR(9 downto 0);
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we : in STD_LOGIC;
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clk : in STD_LOGIC;
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q : out STD_LOGIC_VECTOR(7 downto 0)
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);
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end component;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-- Architecture: begin
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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begin
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begin
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- Header RAM
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-- Header RAM
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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U_Header_RAM : entity work.RAMZ
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U_Header_RAM : entity work.HeaderRam
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generic map
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(
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RAMADDR_W => 10,
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RAMDATA_W => 8
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)
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port map
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port map
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(
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(
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d => hr_data,
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d => hr_data,
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waddr => hr_waddr,
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waddr => hr_waddr,
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raddr => hr_raddr,
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raddr => hr_raddr,
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