| Line 102... |
Line 102... |
signal rd_addr : std_logic_vector(31 downto 0);
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signal rd_addr : std_logic_vector(31 downto 0);
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signal input_rd_cnt : unsigned(5 downto 0);
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signal input_rd_cnt : unsigned(5 downto 0);
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signal rd_en : std_logic;
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signal rd_en : std_logic;
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signal rd_en_d1 : std_logic;
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signal rd_en_d1 : std_logic;
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signal rdaddr : unsigned(31 downto 0);
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signal rdaddr : unsigned(31 downto 0);
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signal bf_dval : std_logic_vector(2 downto 0);
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signal bf_dval : std_logic_vector(3 downto 0);
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signal wr_cnt : unsigned(5 downto 0);
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signal wr_cnt : unsigned(5 downto 0);
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signal dbuf_data : std_logic_vector(11 downto 0);
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signal dbuf_data : std_logic_vector(11 downto 0);
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signal dbuf_q : std_logic_vector(11 downto 0);
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signal dbuf_q : std_logic_vector(11 downto 0);
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signal dbuf_we : std_logic;
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signal dbuf_we : std_logic;
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signal dbuf_waddr : std_logic_vector(6 downto 0);
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signal dbuf_waddr : std_logic_vector(6 downto 0);
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| Line 164... |
Line 164... |
signal fram1_data : std_logic_vector(23 downto 0);
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signal fram1_data : std_logic_vector(23 downto 0);
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signal fram1_q : std_logic_vector(23 downto 0);
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signal fram1_q : std_logic_vector(23 downto 0);
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signal fram1_we : std_logic;
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signal fram1_we : std_logic;
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signal fram1_waddr : std_logic_vector(5 downto 0);
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signal fram1_waddr : std_logic_vector(5 downto 0);
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signal fram1_raddr : std_logic_vector(5 downto 0);
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signal fram1_raddr : std_logic_vector(5 downto 0);
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signal fram1_rd_d : std_logic_vector(7 downto 0);
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signal fram1_rd_d : std_logic_vector(8 downto 0);
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signal fram1_rd : std_logic;
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signal fram1_rd : std_logic;
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signal bf_fifo_empty_d1 : std_logic;
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signal bf_fifo_empty_d1 : std_logic;
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signal rd_started : std_logic;
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signal rd_started : std_logic;
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signal writing_en : std_logic;
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signal writing_en : std_logic;
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| Line 324... |
Line 324... |
-- FRAM read enable
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-- FRAM read enable
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fram1_rd <= '1';
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fram1_rd <= '1';
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end if;
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end if;
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-- increment FRAM1 read address
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-- increment FRAM1 read address
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if fram1_rd_d(3) = '1' then
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if fram1_rd_d(4) = '1' then
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fram1_raddr <= std_logic_vector(unsigned(fram1_raddr) + 1);
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fram1_raddr <= std_logic_vector(unsigned(fram1_raddr) + 1);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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| Line 347... |
Line 347... |
dcto => mdct_data_out,
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dcto => mdct_data_out,
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odv1 => odv1,
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odv1 => odv1,
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dcto1 => dcto1
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dcto1 => dcto1
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);
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);
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mdct_idval <= fram1_rd_d(7);
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mdct_idval <= fram1_rd_d(8);
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R_s <= signed('0' & fram1_q(7 downto 0));
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R_s <= signed('0' & fram1_q(7 downto 0));
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G_s <= signed('0' & fram1_q(15 downto 8));
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G_s <= signed('0' & fram1_q(15 downto 8));
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B_s <= signed('0' & fram1_q(23 downto 16));
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B_s <= signed('0' & fram1_q(23 downto 16));
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