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---- - Krzysztof Gajewski, gajos@opencores.org ----
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---- - Krzysztof Gajewski, gajos@opencores.org ----
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---- k.gajewski@gmail.com ----
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---- k.gajewski@gmail.com ----
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---- ----
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---- ----
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2014 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2019 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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type exponentiator_states is (FIRST_RUN, NOP,
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type exponentiator_states is (FIRST_RUN, NOP,
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READ_DATA_BASE, READ_DATA_MODULUS, READ_DATA_EXPONENT, READ_DATA_RESIDUUM,
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READ_DATA_BASE, READ_DATA_MODULUS, READ_DATA_EXPONENT, READ_DATA_RESIDUUM,
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COUNT_POWER, EXP_Z, SAVE_EXP_Z, EXP_P, SAVE_EXP_P, EXP_CONTROL, EXP_END, SAVE_EXP_MULT,
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COUNT_POWER, EXP_Z, SAVE_EXP_Z, EXP_P, SAVE_EXP_P, EXP_CONTROL, EXP_END, SAVE_EXP_MULT,
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INFO_RESULT, SHOW_RESULT);
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INFO_RESULT, SHOW_RESULT);
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type fin_data_ctrl_states is (NOP, PAD_FAIL, PAD_FAIL_NOP, PAD_FAIL_DECODE,
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type comm_ctrl_states is (NOP, DECODE_IN, READ_DATA, DECODE_READ, DECODE_READ_PROP, MAKE_MOD_EXP,
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DECODE_IN, READ_DATA, DECODE_READ, DECODE_READ_PROP, MAKE_FINALIZE, OUTPUT_DATA, INFO_STATE,
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OUTPUT_DATA, INFO_STATE, TEMPORARY_STATE, DATA_TO_OUT_PROPAGATE, DATA_TO_OUT_PROPAGATE2,
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TEMPORARY_STATE, DATA_TO_OUT_PROPAGATE, DATA_TO_OUT_PROPAGATE2, MOVE_DATA, MOVE_OUTPUT_DATA);
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MOVE_DATA, MOVE_OUTPUT_DATA);
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---- mnemonics for exponentiator
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---- mnemonics for exponentiator
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constant mn_read_base : STD_LOGIC_VECTOR(2 downto 0) := "000";
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constant mn_read_base : STD_LOGIC_VECTOR(2 downto 0) := "000";
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constant mn_read_modulus : STD_LOGIC_VECTOR(2 downto 0) := "001";
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constant mn_read_modulus : STD_LOGIC_VECTOR(2 downto 0) := "001";
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constant mn_read_exponent : STD_LOGIC_VECTOR(2 downto 0) := "010";
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constant mn_read_exponent : STD_LOGIC_VECTOR(2 downto 0) := "010";
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constant mn_read_residuum : STD_LOGIC_VECTOR(2 downto 0) := "011";
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constant mn_read_residuum : STD_LOGIC_VECTOR(2 downto 0) := "011";
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constant mn_count_power : STD_LOGIC_VECTOR(2 downto 0) := "100";
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constant mn_count_power : STD_LOGIC_VECTOR(2 downto 0) := "100";
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constant mn_show_result : STD_LOGIC_VECTOR(2 downto 0) := "101";
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constant mn_show_result : STD_LOGIC_VECTOR(2 downto 0) := "101";
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constant mn_show_status : STD_LOGIC_VECTOR(2 downto 0) := "110";
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constant mn_prepare_for_data : STD_LOGIC_VECTOR(2 downto 0) := "111";
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constant mn_prepare_for_data : STD_LOGIC_VECTOR(2 downto 0) := "111";
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---- addresses for memory data
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---- addresses for memory data
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constant addr_base : STD_LOGIC_VECTOR(3 downto 0) := "0000";
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constant addr_base : STD_LOGIC_VECTOR(3 downto 0) := "0000";
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constant addr_modulus : STD_LOGIC_VECTOR(3 downto 0) := "0010";
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constant addr_modulus : STD_LOGIC_VECTOR(3 downto 0) := "0010";
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