| Line 74... |
Line 74... |
------------------------------------------------------------------
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------------------------------------------------------------------
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constant C_NR_BITS_TOTAL : integer := 1536;
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constant C_NR_BITS_TOTAL : integer := 1536;
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constant C_NR_STAGES_TOTAL : integer := 96;
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constant C_NR_STAGES_TOTAL : integer := 96;
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constant C_NR_STAGES_LOW : integer := 32;
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constant C_NR_STAGES_LOW : integer := 32;
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constant C_SPLIT_PIPELINE : boolean := true;
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constant C_SPLIT_PIPELINE : boolean := true;
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constant C_NR_OP : integer := 4; -- leave on 4 for simulation
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constant C_NR_M : integer := 2; -- leave on 2 for simulation
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constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16
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constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options
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constant C_DEVICE : string := "xilinx"; -- xilinx, altera are valid options
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|
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-- extra calculated constants
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-- extra calculated constants
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constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
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constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
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constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW;
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constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW;
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| Line 552... |
Line 557... |
write(Lw, string'("----- Loading exponent fifo: "));
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write(Lw, string'("----- Loading exponent fifo: "));
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writeline(output, Lw);
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writeline(output, Lw);
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for i in (exponent_width/16)-1 downto 0 loop
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for i in (exponent_width/16)-1 downto 0 loop
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core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16));
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core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16));
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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assert (core_fifo_full='0')
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report "Fifo error, fifo full" severity failure;
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core_fifo_push <= '1';
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core_fifo_push <= '1';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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assert (core_fifo_full='0' and core_fifo_nopush='0')
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assert (core_fifo_full='0' and core_fifo_nopush='0')
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report "Fifo error, full or nopush" severity failure;
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report "Fifo error, fifo nopush" severity failure;
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core_fifo_push <= '0';
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core_fifo_push <= '0';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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end loop;
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end loop;
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waitclk(10);
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waitclk(10);
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write(Lw, string'(" => Done"));
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write(Lw, string'(" => Done"));
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| Line 669... |
Line 676... |
the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
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the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
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generic map(
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generic map(
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C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
|
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C_NR_OP => C_NR_OP,
|
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C_NR_M => C_NR_M,
|
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C_FIFO_DEPTH => C_FIFO_DEPTH,
|
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C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
|
|
C_DEVICE => C_DEVICE -- xilinx, altera are valid options
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)
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)
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port map(
|
port map(
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clk => clk,
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clk => clk,
|
reset => reset,
|
reset => reset,
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-- operand memory interface (plb shared memory)
|
-- operand memory interface (plb shared memory)
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| Line 693... |
Line 705... |
ready => core_ready,
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ready => core_ready,
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x_sel_single => core_x_sel_single,
|
x_sel_single => core_x_sel_single,
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y_sel_single => core_y_sel_single,
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y_sel_single => core_y_sel_single,
|
dest_op_single => core_dest_op_single,
|
dest_op_single => core_dest_op_single,
|
p_sel => core_p_sel,
|
p_sel => core_p_sel,
|
calc_time => calc_time
|
calc_time => calc_time,
|
|
modulus_sel => "0"
|
);
|
);
|
|
|
end test;
|
end test;
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No newline at end of file
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No newline at end of file
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