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[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [mod_sim_exp_core_tb.vhd] - Diff between revs 46 and 70

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Rev 46 Rev 70
Line 74... Line 74...
  ------------------------------------------------------------------
  ------------------------------------------------------------------
  constant C_NR_BITS_TOTAL   : integer := 1536;
  constant C_NR_BITS_TOTAL   : integer := 1536;
  constant C_NR_STAGES_TOTAL : integer := 96;
  constant C_NR_STAGES_TOTAL : integer := 96;
  constant C_NR_STAGES_LOW   : integer := 32;
  constant C_NR_STAGES_LOW   : integer := 32;
  constant C_SPLIT_PIPELINE  : boolean := true;
  constant C_SPLIT_PIPELINE  : boolean := true;
 
  constant C_NR_OP           : integer := 4;  -- leave on 4 for simulation
 
  constant C_NR_M            : integer := 2;  -- leave on 2 for simulation
 
  constant C_FIFO_DEPTH      : integer := 32; -- set to (maximum exponent width)/16
 
  constant C_MEM_STYLE       : string  := "generic"; -- xil_prim, generic, asym are valid options
 
  constant C_DEVICE          : string  := "xilinx";  -- xilinx, altera are valid options
 
 
  -- extra calculated constants
  -- extra calculated constants
  constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
  constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
  constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW;
  constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW;
 
 
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        write(Lw, string'("----- Loading exponent fifo: "));
        write(Lw, string'("----- Loading exponent fifo: "));
        writeline(output, Lw);
        writeline(output, Lw);
        for i in (exponent_width/16)-1 downto 0 loop
        for i in (exponent_width/16)-1 downto 0 loop
          core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16));
          core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16));
          wait until rising_edge(clk);
          wait until rising_edge(clk);
 
          assert (core_fifo_full='0')
 
            report "Fifo error, fifo full" severity failure;
          core_fifo_push <= '1';
          core_fifo_push <= '1';
          wait until rising_edge(clk);
          wait until rising_edge(clk);
          assert (core_fifo_full='0' and core_fifo_nopush='0')
          assert (core_fifo_full='0' and core_fifo_nopush='0')
            report "Fifo error, full or nopush" severity failure;
            report "Fifo error, fifo nopush" severity failure;
          core_fifo_push <= '0';
          core_fifo_push <= '0';
          wait until rising_edge(clk);
          wait until rising_edge(clk);
        end loop;
        end loop;
        waitclk(10);
        waitclk(10);
        write(Lw, string'("  => Done"));
        write(Lw, string'("  => Done"));
Line 669... Line 676...
the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
generic map(
generic map(
  C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
  C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
  C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
  C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
  C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
  C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
  C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE
  C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
 
  C_NR_OP           => C_NR_OP,
 
  C_NR_M            => C_NR_M,
 
  C_FIFO_DEPTH      => C_FIFO_DEPTH,
 
  C_MEM_STYLE       => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
 
  C_DEVICE          => C_DEVICE   -- xilinx, altera are valid options
)
)
port map(
port map(
  clk   => clk,
  clk   => clk,
  reset => reset,
  reset => reset,
-- operand memory interface (plb shared memory)
-- operand memory interface (plb shared memory)
Line 693... Line 705...
  ready          => core_ready,
  ready          => core_ready,
  x_sel_single   => core_x_sel_single,
  x_sel_single   => core_x_sel_single,
  y_sel_single   => core_y_sel_single,
  y_sel_single   => core_y_sel_single,
  dest_op_single => core_dest_op_single,
  dest_op_single => core_dest_op_single,
  p_sel          => core_p_sel,
  p_sel          => core_p_sel,
  calc_time      => calc_time
  calc_time      => calc_time,
 
  modulus_sel    => "0"
);
);
 
 
end test;
end test;
 
 
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