| Line 75... |
Line 75... |
constant C_NR_BITS_TOTAL : integer := 1536;
|
constant C_NR_BITS_TOTAL : integer := 1536;
|
constant C_NR_STAGES_TOTAL : integer := 96;
|
constant C_NR_STAGES_TOTAL : integer := 96;
|
constant C_NR_STAGES_LOW : integer := 32;
|
constant C_NR_STAGES_LOW : integer := 32;
|
constant C_SPLIT_PIPELINE : boolean := true;
|
constant C_SPLIT_PIPELINE : boolean := true;
|
constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16
|
constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16
|
constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options
|
constant C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options
|
constant C_DEVICE : string := "xilinx"; -- xilinx, altera are valid options
|
constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
|
|
|
-- extra calculated constants
|
-- extra calculated constants
|
constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
|
constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
|
constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW;
|
constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW;
|
|
|
| Line 677... |
Line 677... |
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
|
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
|
C_NR_STAGES_LOW => C_NR_STAGES_LOW,
|
C_NR_STAGES_LOW => C_NR_STAGES_LOW,
|
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
|
C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
|
C_FIFO_DEPTH => C_FIFO_DEPTH,
|
C_FIFO_DEPTH => C_FIFO_DEPTH,
|
C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
|
C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
|
C_DEVICE => C_DEVICE -- xilinx, altera are valid options
|
C_FPGA_MAN => C_FPGA_MAN -- xilinx, altera are valid options
|
)
|
)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
-- operand memory interface (plb shared memory)
|
-- operand memory interface (plb shared memory)
|
| Line 702... |
Line 702... |
x_sel_single => core_x_sel_single,
|
x_sel_single => core_x_sel_single,
|
y_sel_single => core_y_sel_single,
|
y_sel_single => core_y_sel_single,
|
dest_op_single => core_dest_op_single,
|
dest_op_single => core_dest_op_single,
|
p_sel => core_p_sel,
|
p_sel => core_p_sel,
|
calc_time => calc_time,
|
calc_time => calc_time,
|
modulus_sel => "0"
|
modulus_sel => '0'
|
);
|
);
|
|
|
end test;
|
end test;
|
|
|
No newline at end of file
|
No newline at end of file
|
