OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [doc/] [src/] [plb_interface.tex] - Diff between revs 87 and 103

Show entire file | Details | Blame | View Log

Rev 87 Rev 103
Line 25... Line 25...
                \rowcolor{Gray}
                \rowcolor{Gray}
                \textbf{Name} & \textbf{Description} & \textbf{VHDL Type} &\textbf{Default Value} \bigstrut\\
                \textbf{Name} & \textbf{Description} & \textbf{VHDL Type} &\textbf{Default Value} \bigstrut\\
                \hline
                \hline
                \multicolumn{4}{|l|}{\textit{\textbf{Memory configuration}}} \\
                \multicolumn{4}{|l|}{\textit{\textbf{Memory configuration}}} \\
                \hline
                \hline
                \verb|C_FIFO_DEPTH| & depth of the generic FIFO, only applicable if \verb|C_MEM_STYLE| = \verb|"generic"| or \verb|"asym"|  & integer & 32 \bigstrut\\
                \verb|C_FIFO_AW| & address width of the generic FIFO pointers, FIFO size is equal to $2^{C\_FIFO\_AW} $. & integer & 7 \bigstrut\\
 
                                                 & only applicable if \verb|C_MEM_STYLE| = \verb|"generic"| or \verb|"asym"|  & & \\
                \hline
                \hline
                \verb|C_MEM_STYLE| & the memory structure to use for the RAM, choice between 3 options: & string & \verb|"generic"| \bigstrut\\
                \verb|C_MEM_STYLE| & the memory structure to use for the RAM, choice between 3 options: & string & \verb|"generic"| \bigstrut\\
                                                        & \verb|"xil_prim"| : use xilinx primitives & & \\
                                                        & \verb|"xil_prim"| : use xilinx primitives & & \\
                                                & \verb|"generic"| : use general 32-bit RAMs & & \\
                                                & \verb|"generic"| : use general 32-bit RAMs & & \\
                                                & \verb|"asym"| : use asymmetric RAMs & & \\
                                                & \verb|"asym"| : use asymmetric RAMs & & \\

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.