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[/] [mod_sim_exp/] [trunk/] [doc/] [src/] [plb_interface.tex] - Diff between revs 78 and 87

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                                                        & \verb|"xil_prim"| : use xilinx primitives & & \\
                                                        & \verb|"xil_prim"| : use xilinx primitives & & \\
                                                & \verb|"generic"| : use general 32-bit RAMs & & \\
                                                & \verb|"generic"| : use general 32-bit RAMs & & \\
                                                & \verb|"asym"| : use asymmetric RAMs & & \\
                                                & \verb|"asym"| : use asymmetric RAMs & & \\
                                                & (For more information see \ref{subsec:RAM_and_FIFO}) & & \bigstrut[b] \\
                                                & (For more information see \ref{subsec:RAM_and_FIFO}) & & \bigstrut[b] \\
                \hline
                \hline
                \verb|C_DEVICE| & device manufacturer: & string & \verb|"xilinx"| \\
                \verb|C_FPGA_MAN| & device manufacturer: & string & \verb|"xilinx"| \\
                                                & \verb|"xilinx"| or \verb|"altera"| &  &  \bigstrut\\
                                                & \verb|"xilinx"| or \verb|"altera"| &  &  \bigstrut\\
                \hline
                \hline
                \verb|C_BASEADDR| & base address for the IP core's memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
                \verb|C_BASEADDR| & base address for the IP core's memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
                \hline
                \hline
                \verb|C_HIGHADDR| & high address for the IP core's memory space & std\_logic\_vector & X"00000000" \bigstrut\\
                \verb|C_HIGHADDR| & high address for the IP core's memory space & std\_logic\_vector & X"00000000" \bigstrut\\

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