------------------------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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---- autorun_ctrl ----
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-- Geoffrey Ottoy - DraMCo research group
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---- ----
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--
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---- This file is part of the ----
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-- Module Name: autorun_cntrl.vhd / entity autorun_cntrl
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---- Modular Simultaneous Exponentiation Core project ----
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--
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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-- Last Modified: 25/04/2012
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---- ----
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--
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---- Description ----
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-- Description: autorun control unit for a pipelined montgomery multiplier
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---- autorun control unit for a pipelined montgomery ----
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--
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---- multiplier ----
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--
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---- ----
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-- Dependencies: none
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---- Dependencies: none ----
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--
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---- ----
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-- Revision 2.00 - Major bug fix: bit_counter should count from 15 downto 0.
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---- Authors: ----
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-- Revision 1.00 - Architecture created
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---- - Geoffrey Ottoy, DraMCo research group ----
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-- Revision 0.01 - File Created
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---- - Jonas De Craene, JonasDC@opencores.org ----
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-- Additional Comments:
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---- ----
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--
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----------------------------------------------------------------------
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--
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---- ----
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------------------------------------------------------------------------------------
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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--
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---- ----
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-- NOTICE:
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---- This source file may be used and distributed without ----
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--
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---- restriction provided that this copyright statement is not ----
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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---- removed from the file and that any derivative work contains ----
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-- by other third parties!
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---- the original copyright notice and the associated disclaimer. ----
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--
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---- ----
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----------------------------------------------------------------------------------
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---- This source file is free software; you can redistribute it ----
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library IEEE;
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---- and/or modify it under the terms of the GNU Lesser General ----
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use IEEE.STD_LOGIC_1164.ALL;
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---- Public License as published by the Free Software Foundation; ----
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use IEEE.STD_LOGIC_ARITH.ALL;
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---- either version 2.1 of the License, or (at your option) any ----
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- later version. ----
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---- ----
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---- Uncomment the following library declaration if instantiating
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---- This source is distributed in the hope that it will be ----
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---- any Xilinx primitives in this code.
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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--library UNISIM;
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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--use UNISIM.VComponents.all;
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity autorun_cntrl is
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entity autorun_cntrl is
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Port ( clk : in STD_LOGIC;
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port (
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reset : in STD_LOGIC;
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clk : in std_logic;
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start : in STD_LOGIC;
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reset : in std_logic;
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done : out STD_LOGIC;
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start : in std_logic;
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op_sel : out STD_LOGIC_VECTOR (1 downto 0);
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done : out std_logic;
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start_multiplier : out STD_LOGIC;
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op_sel : out std_logic_vector (1 downto 0);
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multiplier_done : in STD_LOGIC;
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start_multiplier : out std_logic;
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read_buffer : out STD_LOGIC;
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multiplier_done : in std_logic;
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buffer_din : in STD_LOGIC_VECTOR (31 downto 0);
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read_buffer : out std_logic;
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buffer_empty : in STD_LOGIC);
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buffer_din : in std_logic_vector (31 downto 0);
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buffer_empty : in std_logic
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);
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end autorun_cntrl;
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end autorun_cntrl;
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architecture Behavioral of autorun_cntrl is
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architecture Behavioral of autorun_cntrl is
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signal bit_counter_i : integer range 0 to 15 := 0;
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signal bit_counter_i : integer range 0 to 15 := 0;
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signal bit_counter_0_i : std_logic;
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signal bit_counter_0_i : std_logic;
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signal bit_counter_15_i : std_logic;
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signal bit_counter_15_i : std_logic;
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signal next_bit_i : std_logic := '0';
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signal next_bit_i : std_logic := '0';
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signal next_bit_del_i : std_logic;
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signal next_bit_del_i : std_logic;
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signal start_cycle_i : std_logic := '0';
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signal start_cycle_i : std_logic := '0';
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signal start_cycle_del_i : std_logic;
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signal start_cycle_del_i : std_logic;
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signal done_i : std_logic;
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signal done_i : std_logic;
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signal start_i : std_logic;
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signal start_i : std_logic;
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signal running_i : std_logic;
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signal running_i : std_logic;
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signal start_multiplier_i : std_logic;
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signal start_multiplier_i : std_logic;
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signal start_multiplier_del_i : std_logic;
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signal start_multiplier_del_i : std_logic;
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signal mult_done_del_i : std_logic;
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signal mult_done_del_i : std_logic;
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signal e0_i : std_logic_vector(15 downto 0);
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signal e0_i : std_logic_vector(15 downto 0);
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signal e1_i : std_logic_vector(15 downto 0);
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signal e1_i : std_logic_vector(15 downto 0);
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signal e0_bit_i : std_logic;
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signal e0_bit_i : std_logic;
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signal e1_bit_i : std_logic;
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signal e1_bit_i : std_logic;
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signal e_bits_i : std_logic_vector(1 downto 0);
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signal e_bits_i : std_logic_vector(1 downto 0);
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signal e_bits_0_i : std_logic;
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signal e_bits_0_i : std_logic;
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signal cycle_counter_i : std_logic;
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signal cycle_counter_i : std_logic;
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signal op_sel_sel_i : std_logic;
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signal op_sel_sel_i : std_logic;
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signal op_sel_i : std_logic_vector(1 downto 0);
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signal op_sel_i : std_logic_vector(1 downto 0);
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begin
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begin
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--done <= (multiplier_done and (not running_i)) or (start and buffer_empty);
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done <= done_i;
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done <= done_i;
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-- the two exponents
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-- the two exponents
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e0_i <= buffer_din(15 downto 0);
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e0_i <= buffer_din(15 downto 0);
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e1_i <= buffer_din(31 downto 16);
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e1_i <= buffer_din(31 downto 16);
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-- generate the index to select a single bit from the two exponents
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-- generate the index to select a single bit from the two exponents
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SYNC_BIT_COUNTER: process (clk, reset)
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SYNC_BIT_COUNTER: process (clk, reset)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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bit_counter_i <= 15;
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bit_counter_i <= 15;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if start = '1' then -- make sure we start @ bit 0
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if start = '1' then -- make sure we start @ bit 0
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bit_counter_i <= 15;
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bit_counter_i <= 15;
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elsif next_bit_i = '1' then -- count
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elsif next_bit_i = '1' then -- count
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if bit_counter_i = 0 then
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if bit_counter_i = 0 then
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bit_counter_i <= 15;
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bit_counter_i <= 15;
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else
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else
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bit_counter_i <= bit_counter_i - 1;
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bit_counter_i <= bit_counter_i - 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process SYNC_BIT_COUNTER;
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end process SYNC_BIT_COUNTER;
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-- signal when bit_counter_i = 0
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-- signal when bit_counter_i = 0
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bit_counter_0_i <= '1' when bit_counter_i=0 else '0';
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bit_counter_0_i <= '1' when bit_counter_i=0 else '0';
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bit_counter_15_i <= '1' when bit_counter_i=15 else '0';
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bit_counter_15_i <= '1' when bit_counter_i=15 else '0';
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-- the bits...
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-- the bits...
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e0_bit_i <= e0_i(bit_counter_i);
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e0_bit_i <= e0_i(bit_counter_i);
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e1_bit_i <= e1_i(bit_counter_i);
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e1_bit_i <= e1_i(bit_counter_i);
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e_bits_i <= e0_bit_i & e1_bit_i;
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e_bits_i <= e0_bit_i & e1_bit_i;
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e_bits_0_i <= '1' when (e_bits_i = "00") else '0';
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e_bits_0_i <= '1' when (e_bits_i = "00") else '0';
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-- operand pre-select
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-- operand pre-select
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with e_bits_i select
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with e_bits_i select
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op_sel_i <= "00" when "10", -- gt0
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op_sel_i <= "00" when "10", -- gt0
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"01" when "01", -- gt1
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"01" when "01", -- gt1
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"10" when "11", -- gt01
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"10" when "11", -- gt01
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"11" when others;
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"11" when others;
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-- select operands
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-- select operands
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op_sel_sel_i <= '0' when e_bits_0_i = '1' else (cycle_counter_i);
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op_sel_sel_i <= '0' when e_bits_0_i = '1' else (cycle_counter_i);
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op_sel <= op_sel_i when op_sel_sel_i = '1' else "11";
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op_sel <= op_sel_i when op_sel_sel_i = '1' else "11";
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-- process that drives running_i signal ('1' when in autorun, '0' when not)
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-- process that drives running_i signal ('1' when in autorun, '0' when not)
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RUNNING_PROC: process(clk, reset)
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RUNNING_PROC: process(clk, reset)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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running_i <= '0';
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running_i <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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running_i <= start or (running_i and (not done_i));
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running_i <= start or (running_i and (not done_i));
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end if;
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end if;
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end process RUNNING_PROC;
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end process RUNNING_PROC;
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-- ctrl logic
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-- ctrl logic
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start_multiplier_i <= start_cycle_del_i or (mult_done_del_i and (cycle_counter_i) and (not e_bits_0_i));
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start_multiplier_i <= start_cycle_del_i or (mult_done_del_i and (cycle_counter_i) and (not e_bits_0_i));
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read_buffer <= start_cycle_del_i and bit_counter_15_i and running_i; -- pop new word from fifo when bit_counter is back at '15'
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read_buffer <= start_cycle_del_i and bit_counter_15_i and running_i; -- pop new word from fifo when bit_counter is back at '15'
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start_multiplier <= start_multiplier_del_i and running_i;
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start_multiplier <= start_multiplier_del_i and running_i;
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-- start/stop logic
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-- start/stop logic
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start_cycle_i <= (start and (not buffer_empty)) or next_bit_i; -- start pulse (external or internal)
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start_cycle_i <= (start and (not buffer_empty)) or next_bit_i; -- start pulse (external or internal)
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done_i <= (start and buffer_empty) or (next_bit_i and bit_counter_0_i and buffer_empty); -- stop when buffer is empty
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done_i <= (start and buffer_empty) or (next_bit_i and bit_counter_0_i and buffer_empty); -- stop when buffer is empty
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next_bit_i <= (mult_done_del_i and e_bits_0_i) or (mult_done_del_i and (not e_bits_0_i) and (not cycle_counter_i));
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next_bit_i <= (mult_done_del_i and e_bits_0_i) or (mult_done_del_i and (not e_bits_0_i) and (not cycle_counter_i));
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-- process for delaying signals with 1 clock cycle
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-- process for delaying signals with 1 clock cycle
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DEL_PROC: process(clk)
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DEL_PROC: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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start_multiplier_del_i <= start_multiplier_i;
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start_multiplier_del_i <= start_multiplier_i;
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start_cycle_del_i <= start_cycle_i;
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start_cycle_del_i <= start_cycle_i;
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mult_done_del_i <= multiplier_done;
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mult_done_del_i <= multiplier_done;
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end if;
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end if;
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end process DEL_PROC;
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end process DEL_PROC;
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-- process for delaying signals with 1 clock cycle
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-- process for delaying signals with 1 clock cycle
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CYCLE_CNTR_PROC: process(clk, start)
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CYCLE_CNTR_PROC: process(clk, start)
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begin
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begin
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if start = '1' or reset = '1' then
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if start = '1' or reset = '1' then
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cycle_counter_i <= '0';
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cycle_counter_i <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if (e_bits_0_i = '0') and (multiplier_done = '1') then
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if (e_bits_0_i = '0') and (multiplier_done = '1') then
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cycle_counter_i <= not cycle_counter_i;
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cycle_counter_i <= not cycle_counter_i;
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elsif (e_bits_0_i = '1') and (multiplier_done = '1') then
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elsif (e_bits_0_i = '1') and (multiplier_done = '1') then
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cycle_counter_i <= '0';
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cycle_counter_i <= '0';
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else
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else
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cycle_counter_i <= cycle_counter_i;
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cycle_counter_i <= cycle_counter_i;
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end if;
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end if;
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end if;
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end if;
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end process CYCLE_CNTR_PROC;
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end process CYCLE_CNTR_PROC;
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end Behavioral;
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end Behavioral;
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