| Line 68... |
Line 68... |
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signal bit_counter_i : integer range 0 to 15 := 0;
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signal bit_counter_i : integer range 0 to 15 := 0;
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signal bit_counter_0_i : std_logic;
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signal bit_counter_0_i : std_logic;
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signal bit_counter_15_i : std_logic;
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signal bit_counter_15_i : std_logic;
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signal next_bit_i : std_logic := '0';
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signal next_bit_i : std_logic := '0';
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signal next_bit_del_i : std_logic;
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signal start_cycle_i : std_logic := '0';
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signal start_cycle_i : std_logic := '0';
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signal start_cycle_del_i : std_logic;
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signal start_cycle_del_i : std_logic;
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signal done_i : std_logic;
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signal done_i : std_logic;
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signal start_i : std_logic;
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signal running_i : std_logic;
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signal running_i : std_logic;
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signal start_multiplier_i : std_logic;
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signal start_multiplier_i : std_logic;
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signal start_multiplier_del_i : std_logic;
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signal start_multiplier_del_i : std_logic;
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signal mult_done_del_i : std_logic;
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signal mult_done_del_i : std_logic;
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| Line 166... |
Line 164... |
mult_done_del_i <= multiplier_done;
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mult_done_del_i <= multiplier_done;
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end if;
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end if;
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end process DEL_PROC;
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end process DEL_PROC;
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-- process for delaying signals with 1 clock cycle
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-- process for delaying signals with 1 clock cycle
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CYCLE_CNTR_PROC: process(clk, start)
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CYCLE_CNTR_PROC: process(clk, start, reset)
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begin
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begin
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if start = '1' or reset = '1' then
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if start = '1' or reset = '1' then
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cycle_counter_i <= '0';
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cycle_counter_i <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if (e_bits_0_i = '0') and (multiplier_done = '1') then
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if (e_bits_0_i = '0') and (multiplier_done = '1') then
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