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Line 79... |
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signal start_multiplier_i : std_logic;
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signal start_multiplier_i : std_logic;
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signal start_multiplier_del_i : std_logic;
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signal start_multiplier_del_i : std_logic;
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signal mult_done_del_i : std_logic;
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signal mult_done_del_i : std_logic;
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signal e0_i : std_logic_vector(15 downto 0);
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signal e1_i : std_logic_vector(15 downto 0);
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signal e0_bit_i : std_logic;
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signal e0_bit_i : std_logic;
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signal e1_bit_i : std_logic;
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signal e1_bit_i : std_logic;
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signal e_bits_i : std_logic_vector(1 downto 0);
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signal e_bits_i : std_logic_vector(1 downto 0);
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signal e_bits_0_i : std_logic;
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signal e_bits_0_i : std_logic;
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signal cycle_counter_i : std_logic;
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signal cycle_counter_i : std_logic;
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signal op_sel_sel_i : std_logic;
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signal op_sel_sel_i : std_logic;
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signal op_sel_i : std_logic_vector(1 downto 0);
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signal op_sel_i : std_logic_vector(1 downto 0);
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signal exponent_shift_i : std_logic_vector(31 downto 0);
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signal read_buffer_i : std_logic;
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signal read_buffer_i_d : std_logic;
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begin
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begin
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done <= done_i;
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done <= done_i;
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read_buffer <= read_buffer_i;
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-- the two exponents
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e0_i <= buffer_din(15 downto 0);
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e1_i <= buffer_din(31 downto 16);
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-- generate the index to select a single bit from the two exponents
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-- generate the index to select a single bit from the two exponents
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SYNC_BIT_COUNTER: process (clk, reset)
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SYNC_BIT_COUNTER: process (clk, reset)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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Line 113... |
Line 112... |
bit_counter_i <= bit_counter_i - 1;
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bit_counter_i <= bit_counter_i - 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process SYNC_BIT_COUNTER;
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end process SYNC_BIT_COUNTER;
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-- process that implements the shift register for the exponents
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-- more performant than former mux implementation
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EXP_SHIFTER : process (clk, reset)
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begin
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if reset = '1' then
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exponent_shift_i <= (others => '0');
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elsif rising_edge(clk) then
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read_buffer_i_d <= read_buffer_i; -- delay read_buffer signal one clock
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if read_buffer_i_d = '1' then -- after new buffer read, shift in new bits
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exponent_shift_i <= buffer_din;
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elsif next_bit_i = '1' then -- count
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exponent_shift_i(31 downto 1) <= exponent_shift_i(30 downto 0);
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end if;
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end if;
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end process EXP_SHIFTER;
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-- signal when bit_counter_i = 0
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-- signal when bit_counter_i = 0
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bit_counter_0_i <= '1' when bit_counter_i=0 else '0';
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bit_counter_0_i <= '1' when bit_counter_i=0 else '0';
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bit_counter_15_i <= '1' when bit_counter_i=15 else '0';
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bit_counter_15_i <= '1' when bit_counter_i=15 else '0';
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-- the bits...
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-- the bits...
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e0_bit_i <= e0_i(bit_counter_i);
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e0_bit_i <= exponent_shift_i(15);
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e1_bit_i <= e1_i(bit_counter_i);
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e1_bit_i <= exponent_shift_i(31);
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e_bits_i <= e0_bit_i & e1_bit_i;
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e_bits_i <= e0_bit_i & e1_bit_i;
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e_bits_0_i <= '1' when (e_bits_i = "00") else '0';
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e_bits_0_i <= '1' when (e_bits_i = "00") else '0';
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-- operand pre-select
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-- operand pre-select
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with e_bits_i select
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with e_bits_i select
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end if;
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end if;
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end process RUNNING_PROC;
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end process RUNNING_PROC;
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-- ctrl logic
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-- ctrl logic
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start_multiplier_i <= start_cycle_del_i or (mult_done_del_i and (cycle_counter_i) and (not e_bits_0_i));
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start_multiplier_i <= start_cycle_del_i or (mult_done_del_i and (cycle_counter_i) and (not e_bits_0_i));
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read_buffer <= start_cycle_del_i and bit_counter_15_i and running_i; -- pop new word from fifo when bit_counter is back at '15'
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read_buffer_i <= start_cycle_del_i and bit_counter_15_i and running_i; -- pop new word from fifo when bit_counter is back at '15'
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start_multiplier <= start_multiplier_del_i and running_i;
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start_multiplier <= start_multiplier_del_i and running_i;
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-- start/stop logic
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-- start/stop logic
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start_cycle_i <= (start and (not buffer_empty)) or next_bit_i; -- start pulse (external or internal)
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start_cycle_i <= (start and (not buffer_empty)) or next_bit_i; -- start pulse (external or internal)
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done_i <= (start and buffer_empty) or (next_bit_i and bit_counter_0_i and buffer_empty); -- stop when buffer is empty
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done_i <= (start and buffer_empty) or (next_bit_i and bit_counter_0_i and buffer_empty); -- stop when buffer is empty
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Line 179... |
start_cycle_del_i <= start_cycle_i;
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start_cycle_del_i <= start_cycle_i;
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mult_done_del_i <= multiplier_done;
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mult_done_del_i <= multiplier_done;
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end if;
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end if;
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end process DEL_PROC;
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end process DEL_PROC;
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-- process for delaying signals with 1 clock cycle
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-- process for cycle counter
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CYCLE_CNTR_PROC: process(clk, start, reset)
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CYCLE_CNTR_PROC: process(clk, start, reset)
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begin
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begin
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if start = '1' or reset = '1' then
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if start = '1' or reset = '1' then
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cycle_counter_i <= '0';
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cycle_counter_i <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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end if;
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end if;
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end process CYCLE_CNTR_PROC;
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end process CYCLE_CNTR_PROC;
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end Behavioral;
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end Behavioral;
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