| Line 79... |
Line 79... |
|
|
signal start_multiplier_i : std_logic;
|
signal start_multiplier_i : std_logic;
|
signal start_multiplier_del_i : std_logic;
|
signal start_multiplier_del_i : std_logic;
|
signal mult_done_del_i : std_logic;
|
signal mult_done_del_i : std_logic;
|
|
|
signal e0_i : std_logic_vector(15 downto 0);
|
|
signal e1_i : std_logic_vector(15 downto 0);
|
|
signal e0_bit_i : std_logic;
|
signal e0_bit_i : std_logic;
|
signal e1_bit_i : std_logic;
|
signal e1_bit_i : std_logic;
|
signal e_bits_i : std_logic_vector(1 downto 0);
|
signal e_bits_i : std_logic_vector(1 downto 0);
|
signal e_bits_0_i : std_logic;
|
signal e_bits_0_i : std_logic;
|
signal cycle_counter_i : std_logic;
|
signal cycle_counter_i : std_logic;
|
signal op_sel_sel_i : std_logic;
|
signal op_sel_sel_i : std_logic;
|
signal op_sel_i : std_logic_vector(1 downto 0);
|
signal op_sel_i : std_logic_vector(1 downto 0);
|
|
|
|
signal exponent_shift_i : std_logic_vector(31 downto 0);
|
|
signal read_buffer_i : std_logic;
|
|
signal read_buffer_i_d : std_logic;
|
begin
|
begin
|
|
|
done <= done_i;
|
done <= done_i;
|
|
read_buffer <= read_buffer_i;
|
-- the two exponents
|
|
e0_i <= buffer_din(15 downto 0);
|
|
e1_i <= buffer_din(31 downto 16);
|
|
|
|
-- generate the index to select a single bit from the two exponents
|
-- generate the index to select a single bit from the two exponents
|
SYNC_BIT_COUNTER: process (clk, reset)
|
SYNC_BIT_COUNTER: process (clk, reset)
|
begin
|
begin
|
if reset = '1' then
|
if reset = '1' then
|
| Line 113... |
Line 112... |
bit_counter_i <= bit_counter_i - 1;
|
bit_counter_i <= bit_counter_i - 1;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process SYNC_BIT_COUNTER;
|
end process SYNC_BIT_COUNTER;
|
|
|
|
-- process that implements the shift register for the exponents
|
|
-- more performant than former mux implementation
|
|
EXP_SHIFTER : process (clk, reset)
|
|
begin
|
|
if reset = '1' then
|
|
exponent_shift_i <= (others => '0');
|
|
elsif rising_edge(clk) then
|
|
read_buffer_i_d <= read_buffer_i; -- delay read_buffer signal one clock
|
|
if read_buffer_i_d = '1' then -- after new buffer read, shift in new bits
|
|
exponent_shift_i <= buffer_din;
|
|
elsif next_bit_i = '1' then -- count
|
|
exponent_shift_i(31 downto 1) <= exponent_shift_i(30 downto 0);
|
|
end if;
|
|
end if;
|
|
end process EXP_SHIFTER;
|
|
|
-- signal when bit_counter_i = 0
|
-- signal when bit_counter_i = 0
|
bit_counter_0_i <= '1' when bit_counter_i=0 else '0';
|
bit_counter_0_i <= '1' when bit_counter_i=0 else '0';
|
bit_counter_15_i <= '1' when bit_counter_i=15 else '0';
|
bit_counter_15_i <= '1' when bit_counter_i=15 else '0';
|
-- the bits...
|
-- the bits...
|
e0_bit_i <= e0_i(bit_counter_i);
|
e0_bit_i <= exponent_shift_i(15);
|
e1_bit_i <= e1_i(bit_counter_i);
|
e1_bit_i <= exponent_shift_i(31);
|
e_bits_i <= e0_bit_i & e1_bit_i;
|
e_bits_i <= e0_bit_i & e1_bit_i;
|
e_bits_0_i <= '1' when (e_bits_i = "00") else '0';
|
e_bits_0_i <= '1' when (e_bits_i = "00") else '0';
|
|
|
-- operand pre-select
|
-- operand pre-select
|
with e_bits_i select
|
with e_bits_i select
|
| Line 145... |
Line 161... |
end if;
|
end if;
|
end process RUNNING_PROC;
|
end process RUNNING_PROC;
|
|
|
-- ctrl logic
|
-- ctrl logic
|
start_multiplier_i <= start_cycle_del_i or (mult_done_del_i and (cycle_counter_i) and (not e_bits_0_i));
|
start_multiplier_i <= start_cycle_del_i or (mult_done_del_i and (cycle_counter_i) and (not e_bits_0_i));
|
read_buffer <= start_cycle_del_i and bit_counter_15_i and running_i; -- pop new word from fifo when bit_counter is back at '15'
|
read_buffer_i <= start_cycle_del_i and bit_counter_15_i and running_i; -- pop new word from fifo when bit_counter is back at '15'
|
start_multiplier <= start_multiplier_del_i and running_i;
|
start_multiplier <= start_multiplier_del_i and running_i;
|
|
|
-- start/stop logic
|
-- start/stop logic
|
start_cycle_i <= (start and (not buffer_empty)) or next_bit_i; -- start pulse (external or internal)
|
start_cycle_i <= (start and (not buffer_empty)) or next_bit_i; -- start pulse (external or internal)
|
done_i <= (start and buffer_empty) or (next_bit_i and bit_counter_0_i and buffer_empty); -- stop when buffer is empty
|
done_i <= (start and buffer_empty) or (next_bit_i and bit_counter_0_i and buffer_empty); -- stop when buffer is empty
|
| Line 163... |
Line 179... |
start_cycle_del_i <= start_cycle_i;
|
start_cycle_del_i <= start_cycle_i;
|
mult_done_del_i <= multiplier_done;
|
mult_done_del_i <= multiplier_done;
|
end if;
|
end if;
|
end process DEL_PROC;
|
end process DEL_PROC;
|
|
|
-- process for delaying signals with 1 clock cycle
|
-- process for cycle counter
|
CYCLE_CNTR_PROC: process(clk, start, reset)
|
CYCLE_CNTR_PROC: process(clk, start, reset)
|
begin
|
begin
|
if start = '1' or reset = '1' then
|
if start = '1' or reset = '1' then
|
cycle_counter_i <= '0';
|
cycle_counter_i <= '0';
|
elsif rising_edge(clk) then
|
elsif rising_edge(clk) then
|
| Line 181... |
Line 197... |
end if;
|
end if;
|
end process CYCLE_CNTR_PROC;
|
end process CYCLE_CNTR_PROC;
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
