URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [cell_1b.vhd] - Diff between revs 9 and 14

Rev 9	Rev 14
Line 1...	Line 1...
`----------------------------------------------------------------------`	`----------------------------------------------------------------------`
`---- cel_1b ----`	`---- cell_1b ----`
`---- ----`	`---- ----`
`---- This file is part of the ----`	`---- This file is part of the ----`
`---- Modular Simultaneous Exponentiation Core project ----`	`---- Modular Simultaneous Exponentiation Core project ----`
`---- http://www.opencores.org/cores/mod_sim_exp/ ----`	`---- http://www.opencores.org/cores/mod_sim_exp/ ----`
`---- ----`	`---- ----`
Line 57...	Line 57...
`port (`	`port (`
`-- operand input bits (m+y, y and m)`	`-- operand input bits (m+y, y and m)`
`my : in std_logic;`	`my : in std_logic;`
`y : in std_logic;`	`y : in std_logic;`
`m : in std_logic;`	`m : in std_logic;`
`-- operand x input bit and q (serial)`	`-- operand x input bit and q`
`x : in std_logic;`	`x : in std_logic;`
`q : in std_logic;`	`q : in std_logic;`
`-- previous result input bit`	`-- previous result input bit`
`a : in std_logic;`	`a : in std_logic;`
`-- carry's`	`-- carry's`