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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [cell_1b.vhd] - Diff between revs 3 and 9

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----  This file is part of the                                    ----
----  This file is part of the                                    ----
----    Modular Simultaneous Exponentiation Core project          ---- 
----    Modular Simultaneous Exponentiation Core project          ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----                                                              ---- 
----                                                              ---- 
----  Description                                                 ---- 
----  Description                                                 ---- 
----    1 bit cell for use in the montgommery multiplier systolic ----
----    1-bit cell for use in the montgommery multiplier systolic ----
----    array                                                     ----
----    array                                                     ----
----                                                              ---- 
----                                                              ---- 
----  Dependencies:                                               ---- 
----  Dependencies:                                               ---- 
----    - cell_1bit_adder                                         ---- 
----    - cell_1bit_adder                                         ---- 
----    - cell_1bit_mux                                           ----
----    - cell_1bit_mux                                           ----
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use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
library mod_sim_exp;
library mod_sim_exp;
use mod_sim_exp.mod_sim_exp_pkg.all;
use mod_sim_exp.mod_sim_exp_pkg.all;
 
 
 
-- 1-bit cell for the systolic array
entity cell_1b is
entity cell_1b is
  port (
  port (
 
    -- operand input bits (m+y, y and m)
    my   : in  std_logic;
    my   : in  std_logic;
    y    : in  std_logic;
    y    : in  std_logic;
    m    : in  std_logic;
    m    : in  std_logic;
 
    -- operand x input bit and q (serial)
    x    : in  std_logic;
    x    : in  std_logic;
    q    : in  std_logic;
    q    : in  std_logic;
 
    -- previous result input bit
    a    : in  std_logic;
    a    : in  std_logic;
 
    -- carry's
    cin  : in  std_logic;
    cin  : in  std_logic;
    cout : out std_logic;
    cout : out std_logic;
 
    -- cell result out
    r    : out std_logic
    r    : out std_logic
  );
  );
end cell_1b;
end cell_1b;
 
 
 
 
architecture Structural of cell_1b is
architecture Structural of cell_1b is
 
  -- mux to adder connection
  signal mux2adder : std_logic;
  signal mux2adder : std_logic;
begin
begin
 
 
 
  -- mux for my, y and m input bits
  cell_mux : cell_1b_mux
  cell_mux : cell_1b_mux
  port map(
  port map(
    my     => my,
    my     => my,
    y      => y,
    y      => y,
    m      => m,
    m      => m,
    x      => x,
    x      => x,
    q      => q,
    q      => q,
    result => mux2adder
    result => mux2adder
  );
  );
 
 
 
  -- full adder for a+mux2adder
  cell_adder : cell_1b_adder
  cell_adder : cell_1b_adder
  port map(
  port map(
    a          => a,
    a          => a,
    mux_result => mux2adder,
    b    => mux2adder,
    cin        => cin,
    cin        => cin,
    cout       => cout,
    cout       => cout,
    r          => r
    r          => r
  );
  );
 
 

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