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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [cell_1b_adder.vhd] - Diff between revs 8 and 9

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use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
-- 1-bit full adder cell
-- 1-bit full adder cell
-- for use in the montgommery multiplier systolic array cells
 
entity cell_1b_adder is
entity cell_1b_adder is
  port (
  port (
    a          : in  std_logic;   -- adder input operand a
    -- input operands a, b
    mux_result : in  std_logic;   -- adder input muxed result
    a    : in  std_logic;
    cin        : in  std_logic;   -- carry in
    b    : in  std_logic;
    cout       : out  std_logic;  -- carry out
    -- carry in, out
    r          : out  std_logic   -- result out
    cin  : in  std_logic;
 
    cout : out  std_logic;
 
    -- result out
 
    r    : out  std_logic
  );
  );
end cell_1b_adder;
end cell_1b_adder;
 
 
 
 
architecture Behavioral of cell_1b_adder is
architecture Behavioral of cell_1b_adder is
  signal a_xor_mux_result : std_logic;
  signal a_xor_b : std_logic;
begin
begin
  -- 1-bit full adder with combinatorial logic
  -- 1-bit full adder with combinatorial logic
  -- uses 2 XOR's, 2 AND's and 1 OR port
  -- uses 2 XOR's, 2 AND's and 1 OR port
  a_xor_mux_result <= a xor mux_result;
  a_xor_b <= a xor b;
  r <= a_xor_mux_result xor cin;
  r <= a_xor_b xor cin;
  cout <= (a and mux_result) or (cin and a_xor_mux_result);
  cout <= (a and b) or (cin and a_xor_b);
end Behavioral;
end Behavioral;
 
 
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