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----------------------------------------------------------------------
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---- counter_sync ----
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---- counter_sync ----
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---- ----
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---- ----
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---- This file is part of the ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- counter with synchronous count enable. It generates an ----
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---- counter with synchronous count enable. It generates an ----
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---- overflow when max_value is reached ----
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---- overflow when max_value is reached ----
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---- ----
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---- ----
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---- Dependencies: none ----
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---- Dependencies: none ----
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---- ----
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---- ----
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---- Authors: ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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-- counter with synchronous count enable. It generates an
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-- overflow when max_value is reached
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entity counter_sync is
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entity counter_sync is
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generic(
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generic(
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max_value : integer := 1024
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max_value : integer := 1024 -- maximum value (constraints the nr bits for counter)
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);
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);
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port(
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port(
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reset_value : in integer;
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reset_value : in integer; -- value the counter counts to
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core_clk : in std_logic;
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core_clk : in std_logic; -- clock input
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ce : in std_logic;
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ce : in std_logic; -- count enable
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reset : in std_logic;
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reset : in std_logic; -- reset input
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overflow : out std_logic
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overflow : out std_logic -- gets high when counter reaches reset_value
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);
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);
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end counter_sync;
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end counter_sync;
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architecture Behavioral of counter_sync is
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architecture Behavioral of counter_sync is
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signal overflow_i : std_logic := '0';
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begin
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begin
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overflow <= overflow_i;
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-- counter process with asynchronous active high reset
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count_proc: process(core_clk, ce, reset)
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COUNT_PROC: process(core_clk, ce, reset)
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variable steps_counter : integer range 0 to max_value-1;
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variable steps_counter : integer range 0 to max_value-1 := 0;
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begin
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begin
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if reset = '1' then -- reset counter
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if reset = '1' then -- reset counter
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steps_counter := 0;
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steps_counter := 0;
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overflow_i <= '0';
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overflow <= '0';
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elsif rising_edge(core_clk) then
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elsif rising_edge(core_clk) then
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if ce = '1' then -- count
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-- counter is enabled, count till reset_value
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if ce = '1' then
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if steps_counter = (reset_value-1) then -- generate overflow and reset counter
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if steps_counter = (reset_value-1) then -- generate overflow and reset counter
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steps_counter := 0;
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steps_counter := 0;
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overflow_i <= '1';
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overflow <= '1';
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else -- just count
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else -- just count
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steps_counter := steps_counter + 1;
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steps_counter := steps_counter + 1;
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overflow_i <= '0';
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overflow <= '0';
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end if;
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end if;
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else
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else
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overflow_i <= '0';
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--counter disabled, halt counter
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overflow <= '0';
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steps_counter := steps_counter;
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steps_counter := steps_counter;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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