------------------------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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---- fifo_primitive ----
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-- Geoffrey Ottoy - DraMCo research group
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---- ----
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--
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---- This file is part of the ----
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-- Module Name: adder_n.vhd / entity adder_n
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---- Modular Simultaneous Exponentiation Core project ----
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--
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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-- Last Modified: 04/04/2012
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---- ----
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--
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---- Description ----
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-- Description: 512x32-bit fifo
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---- 512 x 32 bit fifo ----
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--
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---- ----
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--
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---- Dependencies: ----
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-- Dependencies: FIFO18E1 primitive
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---- - FIFO18E1 (xilinx primitive) ----
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--
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---- ----
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-- Revision:
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---- Authors: ----
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-- Revision 1.00 - Architecture
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---- - Geoffrey Ottoy, DraMCo research group ----
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-- Revision 0.01 - File Created
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---- - Jonas De Craene, JonasDC@opencores.org ----
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--
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---- ----
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--
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----------------------------------------------------------------------
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------------------------------------------------------------------------------------
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---- ----
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--
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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-- NOTICE:
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---- ----
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--
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---- This source file may be used and distributed without ----
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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---- restriction provided that this copyright statement is not ----
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-- by other third parties!
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---- removed from the file and that any derivative work contains ----
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--
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---- the original copyright notice and the associated disclaimer. ----
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------------------------------------------------------------------------------------
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---- ----
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library IEEE;
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---- This source file is free software; you can redistribute it ----
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use IEEE.STD_LOGIC_1164.ALL;
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---- and/or modify it under the terms of the GNU Lesser General ----
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use IEEE.STD_LOGIC_ARITH.ALL;
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---- Public License as published by the Free Software Foundation; ----
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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---- Uncomment the following library declaration if instantiating
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-- Xilinx primitives used in this code.
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---- any Xilinx primitives in this code.
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library UNISIM;
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library UNISIM;
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use UNISIM.VComponents.all;
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use UNISIM.VComponents.all;
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entity fifo_primitive is
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entity fifo_primitive is
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Port ( clk : in STD_LOGIC;
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port (
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din : in STD_LOGIC_VECTOR (31 downto 0);
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clk : in std_logic;
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dout : out STD_LOGIC_VECTOR (31 downto 0);
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din : in std_logic_vector (31 downto 0);
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empty : out STD_LOGIC;
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dout : out std_logic_vector (31 downto 0);
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full : out STD_LOGIC;
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empty : out std_logic;
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push : in STD_LOGIC;
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full : out std_logic;
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pop : in STD_LOGIC;
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push : in std_logic;
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reset : in STD_LOGIC;
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pop : in std_logic;
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nopop : out STD_LOGIC;
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reset : in std_logic;
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nopush : out STD_LOGIC
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nopop : out std_logic;
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nopush : out std_logic
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);
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);
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end fifo_primitive;
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end fifo_primitive;
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architecture Behavioral of fifo_primitive is
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architecture Behavioral of fifo_primitive is
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signal rdcount : std_logic_vector(11 downto 0); -- debugging
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signal rdcount : std_logic_vector(11 downto 0); -- debugging
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signal wrcount : std_logic_vector(11 downto 0); -- debugging
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signal wrcount : std_logic_vector(11 downto 0); -- debugging
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signal reset_i, pop_i, push_i, empty_i, full_i, wrerr_i, rderr_i : std_logic;
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signal reset_i, pop_i, push_i, empty_i, full_i, wrerr_i, rderr_i : std_logic;
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begin
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begin
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empty <= empty_i;
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empty <= empty_i;
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full <= full_i;
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full <= full_i;
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-- these logical equations need to be extended where necessary
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-- these logical equations need to be extended where necessary
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nopop <= rderr_i or (pop and reset_i);
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nopop <= rderr_i or (pop and reset_i);
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nopush <= wrerr_i or (push and reset_i);
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nopush <= wrerr_i or (push and reset_i);
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pop_i <= pop and (not reset_i);
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pop_i <= pop and (not reset_i);
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push_i <= push and (not reset_i);
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push_i <= push and (not reset_i);
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-- makes the reset at least three clk_cycles long
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-- makes the reset at least three clk_cycles long
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RESET_PROC: process (reset, clk)
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RESET_PROC: process (reset, clk)
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variable clk_counter : integer range 0 to 3 := 3;
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variable clk_counter : integer range 0 to 3 := 3;
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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reset_i <= '1';
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reset_i <= '1';
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clk_counter := 3;
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clk_counter := 3;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if clk_counter = 0 then
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if clk_counter = 0 then
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clk_counter := 0;
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clk_counter := 0;
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reset_i <= '0';
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reset_i <= '0';
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else
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else
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clk_counter := clk_counter - 1;
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clk_counter := clk_counter - 1;
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reset_i <= '1';
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reset_i <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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FIFO18E1_inst : FIFO18E1
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FIFO18E1_inst : FIFO18E1
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generic map (
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generic map (
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ALMOST_EMPTY_OFFSET => X"00080", -- Sets the almost empty threshold
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ALMOST_EMPTY_OFFSET => X"00080", -- Sets the almost empty threshold
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ALMOST_FULL_OFFSET => X"00080", -- Sets almost full threshold
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ALMOST_FULL_OFFSET => X"00080", -- Sets almost full threshold
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DATA_WIDTH => 36, -- Sets data width to 4, 9, 18, or 36
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DATA_WIDTH => 36, -- Sets data width to 4, 9, 18, or 36
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DO_REG => 1, -- Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE"
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DO_REG => 1, -- Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE"
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EN_SYN => TRUE, -- Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE")
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EN_SYN => TRUE, -- Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE")
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FIFO_MODE => "FIFO18_36", -- Sets mode to FIFO18 or FIFO18_36
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FIFO_MODE => "FIFO18_36", -- Sets mode to FIFO18 or FIFO18_36
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FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to "TRUE" or "FALSE"
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FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to "TRUE" or "FALSE"
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INIT => X"000000000", -- Initial values on output port
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INIT => X"000000000", -- Initial values on output port
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SRVAL => X"000000000" -- Set/Reset value for output port
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SRVAL => X"000000000" -- Set/Reset value for output port
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)
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)
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port map (
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port map (
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-- ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit almost empty output flag
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-- ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit almost empty output flag
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-- ALMOSTFULL => ALMOSTFULL, -- 1-bit almost full output flag
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-- ALMOSTFULL => ALMOSTFULL, -- 1-bit almost full output flag
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DO => dout, -- 32-bit data output
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DO => dout, -- 32-bit data output
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-- DOP => DOP, -- 4-bit parity data output
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-- DOP => DOP, -- 4-bit parity data output
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EMPTY => empty_i, -- 1-bit empty output flag
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EMPTY => empty_i, -- 1-bit empty output flag
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FULL => full_i, -- 1-bit full output flag
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FULL => full_i, -- 1-bit full output flag
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-- WRCOUNT, RDCOUNT: 12-bit (each) FIFO pointers
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-- WRCOUNT, RDCOUNT: 12-bit (each) FIFO pointers
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RDCOUNT => RDCOUNT, -- 12-bit read count output
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RDCOUNT => RDCOUNT, -- 12-bit read count output
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WRCOUNT => WRCOUNT, -- 12-bit write count output
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WRCOUNT => WRCOUNT, -- 12-bit write count output
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-- WRERR, RDERR: 1-bit (each) FIFO full or empty error
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-- WRERR, RDERR: 1-bit (each) FIFO full or empty error
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RDERR => rderr_i, -- 1-bit read error output
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RDERR => rderr_i, -- 1-bit read error output
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WRERR => wrerr_i, -- 1-bit write error
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WRERR => wrerr_i, -- 1-bit write error
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DI => din, -- 32-bit data input
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DI => din, -- 32-bit data input
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DIP => "0000", -- 4-bit parity input
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DIP => "0000", -- 4-bit parity input
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RDEN => pop_i, -- 1-bit read enable input
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RDEN => pop_i, -- 1-bit read enable input
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REGCE => '1', -- 1-bit clock enable input
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REGCE => '1', -- 1-bit clock enable input
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RST => reset_i, -- 1-bit reset input
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RST => reset_i, -- 1-bit reset input
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RSTREG => reset_i, -- 1-bit output register set/reset
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RSTREG => reset_i, -- 1-bit output register set/reset
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-- WRCLK, RDCLK: 1-bit (each) Clocks
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-- WRCLK, RDCLK: 1-bit (each) Clocks
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RDCLK => clk, -- 1-bit read clock input
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RDCLK => clk, -- 1-bit read clock input
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WRCLK => clk, -- 1-bit write clock input
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WRCLK => clk, -- 1-bit write clock input
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WREN => push_i -- 1-bit write enable input
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WREN => push_i -- 1-bit write enable input
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);
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);
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end Behavioral;
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end Behavioral;
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No newline at end of file
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No newline at end of file
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