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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [fifo_primitive.vhd] - Diff between revs 90 and 94

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Rev 90 Rev 94
Line 52... Line 52...
use UNISIM.VComponents.all;
use UNISIM.VComponents.all;
 
 
 
 
entity fifo_primitive is
entity fifo_primitive is
  port (
  port (
    clk    : in  std_logic;
    push_clk : in  std_logic;
 
    pop_clk  : in  std_logic;
    din    : in  std_logic_vector (31 downto 0);
    din    : in  std_logic_vector (31 downto 0);
    dout   : out  std_logic_vector (31 downto 0);
    dout   : out  std_logic_vector (31 downto 0);
    empty  : out  std_logic;
    empty  : out  std_logic;
    full   : out  std_logic;
    full   : out  std_logic;
    push   : in  std_logic;
    push   : in  std_logic;
Line 84... Line 85...
 
 
        pop_i <= pop and (not reset_i);
        pop_i <= pop and (not reset_i);
        push_i <= push and (not reset_i);
        push_i <= push and (not reset_i);
 
 
        -- makes the reset at least three clk_cycles long
        -- makes the reset at least three clk_cycles long
        RESET_PROC: process (reset, clk)
        RESET_PROC: process (reset, push_clk)
                variable clk_counter : integer range 0 to 3 := 3;
                variable clk_counter : integer range 0 to 3 := 3;
        begin
        begin
                if reset = '1' then
                if reset = '1' then
                        reset_i <= '1';
                        reset_i <= '1';
                        clk_counter := 3;
                        clk_counter := 3;
                elsif rising_edge(clk) then
                elsif rising_edge(push_clk) then
                        if clk_counter = 0 then
                        if clk_counter = 0 then
                                clk_counter := 0;
                                clk_counter := 0;
                                reset_i <= '0';
                                reset_i <= '0';
                        else
                        else
                                clk_counter := clk_counter - 1;
                                clk_counter := clk_counter - 1;
Line 107... Line 108...
   generic map (
   generic map (
      ALMOST_EMPTY_OFFSET => X"00080",  -- Sets the almost empty threshold
      ALMOST_EMPTY_OFFSET => X"00080",  -- Sets the almost empty threshold
      ALMOST_FULL_OFFSET => X"00080",   -- Sets almost full threshold
      ALMOST_FULL_OFFSET => X"00080",   -- Sets almost full threshold
      DATA_WIDTH => 36,                 -- Sets data width to 4, 9, 18, or 36
      DATA_WIDTH => 36,                 -- Sets data width to 4, 9, 18, or 36
      DO_REG => 1,                      -- Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE" 
      DO_REG => 1,                      -- Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE" 
      EN_SYN => TRUE,                   -- Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE")
      EN_SYN => FALSE,                   -- Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE")
      FIFO_MODE => "FIFO18_36",         -- Sets mode to FIFO18 or FIFO18_36
      FIFO_MODE => "FIFO18_36",         -- Sets mode to FIFO18 or FIFO18_36
      FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to "TRUE" or "FALSE" 
      FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to "TRUE" or "FALSE" 
      INIT => X"000000000",             -- Initial values on output port
      INIT => X"000000000",             -- Initial values on output port
      SRVAL => X"000000000"             -- Set/Reset value for output port
      SRVAL => X"000000000"             -- Set/Reset value for output port
   )
   )
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      RDEN => pop_i,                -- 1-bit read enable input
      RDEN => pop_i,                -- 1-bit read enable input
      REGCE => '1',                 -- 1-bit clock enable input
      REGCE => '1',                 -- 1-bit clock enable input
      RST => reset_i,               -- 1-bit reset input
      RST => reset_i,               -- 1-bit reset input
      RSTREG => reset_i,            -- 1-bit output register set/reset
      RSTREG => reset_i,            -- 1-bit output register set/reset
      -- WRCLK, RDCLK: 1-bit (each) Clocks
      -- WRCLK, RDCLK: 1-bit (each) Clocks
      RDCLK => clk,                 -- 1-bit read clock input
      RDCLK => pop_clk,                 -- 1-bit read clock input
      WRCLK => clk,                 -- 1-bit write clock input
      WRCLK => push_clk,                 -- 1-bit write clock input
      WREN => push_i                -- 1-bit write enable input
      WREN => push_i                -- 1-bit write enable input
   );
   );
 
 
end Behavioral;
end Behavioral;
 
 
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