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use UNISIM.VComponents.all;
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use UNISIM.VComponents.all;
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entity fifo_primitive is
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entity fifo_primitive is
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port (
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port (
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clk : in std_logic;
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push_clk : in std_logic;
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pop_clk : in std_logic;
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din : in std_logic_vector (31 downto 0);
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din : in std_logic_vector (31 downto 0);
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dout : out std_logic_vector (31 downto 0);
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dout : out std_logic_vector (31 downto 0);
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empty : out std_logic;
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empty : out std_logic;
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full : out std_logic;
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full : out std_logic;
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push : in std_logic;
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push : in std_logic;
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pop_i <= pop and (not reset_i);
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pop_i <= pop and (not reset_i);
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push_i <= push and (not reset_i);
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push_i <= push and (not reset_i);
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-- makes the reset at least three clk_cycles long
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-- makes the reset at least three clk_cycles long
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RESET_PROC: process (reset, clk)
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RESET_PROC: process (reset, push_clk)
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variable clk_counter : integer range 0 to 3 := 3;
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variable clk_counter : integer range 0 to 3 := 3;
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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reset_i <= '1';
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reset_i <= '1';
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clk_counter := 3;
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clk_counter := 3;
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elsif rising_edge(clk) then
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elsif rising_edge(push_clk) then
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if clk_counter = 0 then
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if clk_counter = 0 then
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clk_counter := 0;
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clk_counter := 0;
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reset_i <= '0';
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reset_i <= '0';
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else
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else
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clk_counter := clk_counter - 1;
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clk_counter := clk_counter - 1;
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generic map (
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generic map (
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ALMOST_EMPTY_OFFSET => X"00080", -- Sets the almost empty threshold
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ALMOST_EMPTY_OFFSET => X"00080", -- Sets the almost empty threshold
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ALMOST_FULL_OFFSET => X"00080", -- Sets almost full threshold
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ALMOST_FULL_OFFSET => X"00080", -- Sets almost full threshold
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DATA_WIDTH => 36, -- Sets data width to 4, 9, 18, or 36
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DATA_WIDTH => 36, -- Sets data width to 4, 9, 18, or 36
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DO_REG => 1, -- Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE"
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DO_REG => 1, -- Enable output register (0 or 1) Must be 1 if EN_SYN = "FALSE"
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EN_SYN => TRUE, -- Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE")
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EN_SYN => FALSE, -- Specifies FIFO as dual-clock ("FALSE") or Synchronous ("TRUE")
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FIFO_MODE => "FIFO18_36", -- Sets mode to FIFO18 or FIFO18_36
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FIFO_MODE => "FIFO18_36", -- Sets mode to FIFO18 or FIFO18_36
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FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to "TRUE" or "FALSE"
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FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to "TRUE" or "FALSE"
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INIT => X"000000000", -- Initial values on output port
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INIT => X"000000000", -- Initial values on output port
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SRVAL => X"000000000" -- Set/Reset value for output port
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SRVAL => X"000000000" -- Set/Reset value for output port
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)
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)
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RDEN => pop_i, -- 1-bit read enable input
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RDEN => pop_i, -- 1-bit read enable input
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REGCE => '1', -- 1-bit clock enable input
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REGCE => '1', -- 1-bit clock enable input
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RST => reset_i, -- 1-bit reset input
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RST => reset_i, -- 1-bit reset input
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RSTREG => reset_i, -- 1-bit output register set/reset
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RSTREG => reset_i, -- 1-bit output register set/reset
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-- WRCLK, RDCLK: 1-bit (each) Clocks
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-- WRCLK, RDCLK: 1-bit (each) Clocks
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RDCLK => clk, -- 1-bit read clock input
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RDCLK => pop_clk, -- 1-bit read clock input
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WRCLK => clk, -- 1-bit write clock input
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WRCLK => push_clk, -- 1-bit write clock input
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WREN => push_i -- 1-bit write enable input
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WREN => push_i -- 1-bit write enable input
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);
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);
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end Behavioral;
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end Behavioral;
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