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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_core.vhd] - Diff between revs 36 and 37

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Line 85... Line 85...
  );
  );
end mod_sim_exp_core;
end mod_sim_exp_core;
 
 
 
 
architecture Structural of mod_sim_exp_core is
architecture Structural of mod_sim_exp_core is
  constant n : integer := 1536;
 
  constant t : integer := 96;
 
  constant tl : integer := 32;
 
 
 
  -- data busses
  -- data busses
  signal xy   : std_logic_vector(n-1 downto 0);  -- x and y operand data bus RAM -> multiplier
  signal xy   : std_logic_vector(nr_bits_total-1 downto 0);  -- x and y operand data bus RAM -> multiplier
  signal m    : std_logic_vector(n-1 downto 0);  -- modulus data bus RAM -> multiplier
  signal m    : std_logic_vector(nr_bits_total-1 downto 0);  -- modulus data bus RAM -> multiplier
  signal r    : std_logic_vector(n-1 downto 0);  -- result data bus RAM <- multiplier
  signal r    : std_logic_vector(nr_bits_total-1 downto 0);  -- result data bus RAM <- multiplier
 
 
  -- control signals
  -- control signals
  signal op_sel           : std_logic_vector(1 downto 0); -- operand selection 
  signal op_sel           : std_logic_vector(1 downto 0); -- operand selection 
  signal result_dest_op   : std_logic_vector(1 downto 0); -- result destination operand
  signal result_dest_op   : std_logic_vector(1 downto 0); -- result destination operand
  signal mult_ready       : std_logic;
  signal mult_ready       : std_logic;
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begin
begin
 
 
  -- The actual multiplier
  -- The actual multiplier
  the_multiplier : mont_multiplier
  the_multiplier : mont_multiplier
  generic map(
  generic map(
    n          => n,
    n  => nr_bits_total,
    nr_stages  => t, --(divides n, bits_low & (n-bits_low))
    t  => nr_stages_total,
    stages_low => tl
    tl => nr_stages_low,
 
    split => split_pipeline
  )
  )
  port map(
  port map(
    core_clk => clk,
    core_clk => clk,
    xy       => xy,
    xy       => xy,
    m        => m,
    m        => m,
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  );
  );
 
 
  -- Block ram memory for storing the operands and the modulus
  -- Block ram memory for storing the operands and the modulus
  the_memory : operand_mem
  the_memory : operand_mem
  generic map(
  generic map(
    n => n
    n => nr_bits_total
  )
  )
  port map(
  port map(
    data_in        => data_in,
    data_in        => data_in,
    data_out       => data_out,
    data_out       => data_out,
    rw_address     => rw_address,
    rw_address     => rw_address,

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