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https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_core.vhd] - Diff between revs 36 and 37
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| Rev 36 |
Rev 37 |
| Line 85... |
Line 85... |
);
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);
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end mod_sim_exp_core;
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end mod_sim_exp_core;
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architecture Structural of mod_sim_exp_core is
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architecture Structural of mod_sim_exp_core is
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constant n : integer := 1536;
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constant t : integer := 96;
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constant tl : integer := 32;
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-- data busses
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-- data busses
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signal xy : std_logic_vector(n-1 downto 0); -- x and y operand data bus RAM -> multiplier
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signal xy : std_logic_vector(nr_bits_total-1 downto 0); -- x and y operand data bus RAM -> multiplier
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signal m : std_logic_vector(n-1 downto 0); -- modulus data bus RAM -> multiplier
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signal m : std_logic_vector(nr_bits_total-1 downto 0); -- modulus data bus RAM -> multiplier
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signal r : std_logic_vector(n-1 downto 0); -- result data bus RAM <- multiplier
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signal r : std_logic_vector(nr_bits_total-1 downto 0); -- result data bus RAM <- multiplier
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-- control signals
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-- control signals
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signal op_sel : std_logic_vector(1 downto 0); -- operand selection
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signal op_sel : std_logic_vector(1 downto 0); -- operand selection
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signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand
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signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand
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signal mult_ready : std_logic;
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signal mult_ready : std_logic;
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begin
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begin
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-- The actual multiplier
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-- The actual multiplier
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the_multiplier : mont_multiplier
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the_multiplier : mont_multiplier
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generic map(
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generic map(
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n => n,
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n => nr_bits_total,
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nr_stages => t, --(divides n, bits_low & (n-bits_low))
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t => nr_stages_total,
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stages_low => tl
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tl => nr_stages_low,
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split => split_pipeline
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)
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)
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port map(
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port map(
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core_clk => clk,
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core_clk => clk,
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xy => xy,
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xy => xy,
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m => m,
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m => m,
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);
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);
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-- Block ram memory for storing the operands and the modulus
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-- Block ram memory for storing the operands and the modulus
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the_memory : operand_mem
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the_memory : operand_mem
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generic map(
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generic map(
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n => n
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n => nr_bits_total
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)
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)
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port map(
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port map(
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data_in => data_in,
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data_in => data_in,
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data_out => data_out,
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data_out => data_out,
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rw_address => rw_address,
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rw_address => rw_address,
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