| Line 65... |
Line 65... |
C_NR_STAGES_TOTAL : integer := 96;
|
C_NR_STAGES_TOTAL : integer := 96;
|
C_NR_STAGES_LOW : integer := 32;
|
C_NR_STAGES_LOW : integer := 32;
|
C_SPLIT_PIPELINE : boolean := true;
|
C_SPLIT_PIPELINE : boolean := true;
|
C_NR_OP : integer := 4;
|
C_NR_OP : integer := 4;
|
C_NR_M : integer := 2;
|
C_NR_M : integer := 2;
|
C_FIFO_DEPTH : integer := 32
|
C_FIFO_DEPTH : integer := 32;
|
|
C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options
|
|
C_DEVICE : string := "xilinx" -- xilinx, altera are valid options
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
-- operand memory interface (plb shared memory)
|
-- operand memory interface (plb shared memory)
|
| Line 90... |
Line 92... |
x_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication x operand selection
|
x_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication x operand selection
|
y_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication y operand selection
|
y_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication y operand selection
|
dest_op_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- result destination operand selection
|
dest_op_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- result destination operand selection
|
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
|
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
|
calc_time : out std_logic;
|
calc_time : out std_logic;
|
modulus_sel : in std_logic_vector(log2(C_NR_M)-1 downto 0)
|
modulus_sel : in std_logic_vector(log2(C_NR_M)-1 downto 0) -- selects which modulus to use for multiplications
|
);
|
);
|
end mod_sim_exp_core;
|
end mod_sim_exp_core;
|
|
|
|
|
architecture Structural of mod_sim_exp_core is
|
architecture Structural of mod_sim_exp_core is
|
| Line 137... |
Line 139... |
load_x => load_x,
|
load_x => load_x,
|
ready => mult_ready
|
ready => mult_ready
|
);
|
);
|
|
|
-- Block ram memory for storing the operands and the modulus
|
-- Block ram memory for storing the operands and the modulus
|
the_memory : operand_mem_gen
|
the_memory : operand_mem
|
generic map(
|
generic map(
|
width => C_NR_BITS_TOTAL,
|
width => C_NR_BITS_TOTAL,
|
nr_op => C_NR_OP,
|
nr_op => C_NR_OP,
|
nr_m => C_NR_M
|
nr_m => C_NR_M,
|
|
mem_style => C_MEM_STYLE,
|
|
device => C_DEVICE
|
)
|
)
|
port map(
|
port map(
|
data_in => data_in,
|
data_in => data_in,
|
data_out => data_out,
|
data_out => data_out,
|
rw_address => rw_address,
|
rw_address => rw_address,
|
| Line 161... |
Line 165... |
modulus_sel => modulus_sel
|
modulus_sel => modulus_sel
|
);
|
);
|
|
|
result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3
|
result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3
|
|
|
-- A fifo for auto-run operand selection
|
-- A fifo for exponentiation mode
|
|
xil_prim_fifo : if C_MEM_STYLE="xil_prim" generate
|
|
the_exponent_fifo : fifo_primitive
|
|
port map(
|
|
clk => clk,
|
|
din => fifo_din,
|
|
dout => fifo_dout,
|
|
empty => fifo_empty,
|
|
full => fifo_full,
|
|
push => fifo_push,
|
|
pop => fifo_pop,
|
|
reset => reset,
|
|
nopop => fifo_nopop,
|
|
nopush => fifo_nopush
|
|
);
|
|
end generate;
|
|
gen_fifo : if (C_MEM_STYLE="generic") or (C_MEM_STYLE="asym") generate
|
the_exponent_fifo : fifo_generic
|
the_exponent_fifo : fifo_generic
|
generic map(
|
generic map(
|
depth => C_FIFO_DEPTH
|
depth => C_FIFO_DEPTH
|
)
|
)
|
port map(
|
port map(
|
| Line 178... |
Line 198... |
pop => fifo_pop,
|
pop => fifo_pop,
|
reset => reset,
|
reset => reset,
|
nopop => fifo_nopop,
|
nopop => fifo_nopop,
|
nopush => fifo_nopush
|
nopush => fifo_nopush
|
);
|
);
|
|
end generate;
|
|
|
-- The control logic for the core
|
-- The control logic for the core
|
the_control_unit : mont_ctrl
|
the_control_unit : mont_ctrl
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
