| Line 63... |
Line 63... |
generic(
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generic(
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_LOW : integer := 32;
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C_NR_STAGES_LOW : integer := 32;
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C_SPLIT_PIPELINE : boolean := true;
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C_SPLIT_PIPELINE : boolean := true;
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C_NR_OP : integer := 4;
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C_NR_M : integer := 2;
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C_FIFO_DEPTH : integer := 32;
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C_FIFO_DEPTH : integer := 32;
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C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options
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C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options
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C_DEVICE : string := "xilinx" -- xilinx, altera are valid options
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C_DEVICE : string := "xilinx" -- xilinx, altera are valid options
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- operand memory interface (plb shared memory)
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-- operand memory interface (plb shared memory)
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write_enable : in std_logic; -- write data to operand ram
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write_enable : in std_logic; -- write data to operand ram
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data_in : in std_logic_vector (31 downto 0); -- operand ram data in
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data_in : in std_logic_vector (31 downto 0); -- operand ram data in
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rw_address : in std_logic_vector (log2(C_NR_OP)+log2(C_NR_BITS_TOTAL/32) downto 0); -- operand ram address bus
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rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
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data_out : out std_logic_vector (31 downto 0); -- operand ram data out
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data_out : out std_logic_vector (31 downto 0); -- operand ram data out
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collision : out std_logic; -- write collision
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collision : out std_logic; -- write collision
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-- op_sel fifo interface
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-- op_sel fifo interface
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fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
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fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
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fifo_push : in std_logic; -- push data in exponent fifo
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fifo_push : in std_logic; -- push data in exponent fifo
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| Line 87... |
Line 85... |
fifo_nopush : out std_logic; -- high if error during push
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fifo_nopush : out std_logic; -- high if error during push
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-- control signals
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-- control signals
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start : in std_logic; -- start multiplication/exponentiation
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start : in std_logic; -- start multiplication/exponentiation
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exp_m : in std_logic; -- single multiplication if low, exponentiation if high
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exp_m : in std_logic; -- single multiplication if low, exponentiation if high
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ready : out std_logic; -- calculations done
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ready : out std_logic; -- calculations done
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x_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication x operand selection
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x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
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y_sel_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- single multiplication y operand selection
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y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
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dest_op_single : in std_logic_vector (log2(C_NR_OP)-1 downto 0); -- result destination operand selection
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dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
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p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
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p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
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calc_time : out std_logic;
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calc_time : out std_logic;
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modulus_sel : in std_logic_vector(log2(C_NR_M)-1 downto 0) -- selects which modulus to use for multiplications
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modulus_sel : in std_logic -- selects which modulus to use for multiplications
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);
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);
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end mod_sim_exp_core;
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end mod_sim_exp_core;
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|
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|
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architecture Structural of mod_sim_exp_core is
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architecture Structural of mod_sim_exp_core is
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-- constants
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constant nr_op : integer := 4;
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constant nr_m : integer := 2;
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|
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-- data busses
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-- data busses
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signal xy : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- x and y operand data bus RAM -> multiplier
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signal xy : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- x and y operand data bus RAM -> multiplier
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signal m : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- modulus data bus RAM -> multiplier
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signal m : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- modulus data bus RAM -> multiplier
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signal r : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- result data bus RAM <- multiplier
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signal r : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0); -- result data bus RAM <- multiplier
|
|
|
| Line 110... |
Line 112... |
signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand
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signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand
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signal mult_ready : std_logic;
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signal mult_ready : std_logic;
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signal start_mult : std_logic;
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signal start_mult : std_logic;
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signal load_x : std_logic;
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signal load_x : std_logic;
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signal load_result : std_logic;
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signal load_result : std_logic;
|
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signal modulus_sel_i : std_logic_vector(0 downto 0);
|
|
|
-- fifo signals
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-- fifo signals
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signal fifo_empty : std_logic;
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signal fifo_empty : std_logic;
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signal fifo_pop : std_logic;
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signal fifo_pop : std_logic;
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signal fifo_nopop : std_logic;
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signal fifo_nopop : std_logic;
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| Line 142... |
Line 145... |
|
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-- Block ram memory for storing the operands and the modulus
|
-- Block ram memory for storing the operands and the modulus
|
the_memory : operand_mem
|
the_memory : operand_mem
|
generic map(
|
generic map(
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width => C_NR_BITS_TOTAL,
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width => C_NR_BITS_TOTAL,
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nr_op => C_NR_OP,
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nr_op => nr_op,
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nr_m => C_NR_M,
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nr_m => nr_m,
|
mem_style => C_MEM_STYLE,
|
mem_style => C_MEM_STYLE,
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device => C_DEVICE
|
device => C_DEVICE
|
)
|
)
|
port map(
|
port map(
|
data_in => data_in,
|
data_in => data_in,
|
| Line 160... |
Line 163... |
result_in => r,
|
result_in => r,
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load_result => load_result,
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load_result => load_result,
|
result_dest_op => result_dest_op,
|
result_dest_op => result_dest_op,
|
collision => collision,
|
collision => collision,
|
clk => clk,
|
clk => clk,
|
modulus_sel => modulus_sel
|
modulus_sel => modulus_sel_i
|
);
|
);
|
|
|
|
modulus_sel_i(0) <= modulus_sel;
|
result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3
|
result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3
|
|
|
-- A fifo for exponentiation mode
|
-- A fifo for exponentiation mode
|
xil_prim_fifo : if C_MEM_STYLE="xil_prim" generate
|
xil_prim_fifo : if C_MEM_STYLE="xil_prim" generate
|
the_exponent_fifo : fifo_primitive
|
the_exponent_fifo : fifo_primitive
|
