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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_core.vhd] - Diff between revs 74 and 75
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| Rev 74 |
Rev 75 |
| Line 64... |
Line 64... |
C_NR_BITS_TOTAL : integer := 1536;
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C_NR_BITS_TOTAL : integer := 1536;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_TOTAL : integer := 96;
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C_NR_STAGES_LOW : integer := 32;
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C_NR_STAGES_LOW : integer := 32;
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C_SPLIT_PIPELINE : boolean := true;
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C_SPLIT_PIPELINE : boolean := true;
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C_FIFO_DEPTH : integer := 32;
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C_FIFO_DEPTH : integer := 32;
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C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options
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C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options
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C_DEVICE : string := "xilinx" -- xilinx, altera are valid options
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C_DEVICE : string := "xilinx" -- xilinx, altera are valid options
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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